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{{lithography processes}}
 
{{lithography processes}}
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The '''250 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[350 nm lithography process|350 nm process]] node. Commercial [[integrated circuit]] manufacturing using 250 nm process began in 1997 and was eventually replaced by [[180 nm]] by 1999.
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The '''250 nanometer (250 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[350 nm lithography process|350 nm process]] node. Commercial [[integrated circuit]] manufacturing using 250 nm process began in 1997 and was eventually replaced by [[180 nm]] by 1999.
  
 
== Industry ==
 
== Industry ==
−
The 0.25 µm-based process entered production at [[Intel]] in 1997. Intel original 0.25 micron process was named ''P856'' or ''Process 856''. A second process, named ''P856.5'', was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm<sup>2</sup>, 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO<sub>2</sub>]] dielectric and [[wikipedia:polysilicon|polysilicon]] electode. It used [[wikipedia:Aluminium|Al]] inter-connects and an [[wikipedia:Silicon|Si]] channels.
+
The 0.25 µm-based process entered production at [[Intel]] in 1997. Intel original 0.25 micron process was named ''P856'' or ''Process 856''. A second process, named ''P856.5'', was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm², 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO<sub>2</sub>]] dielectric and [[wikipedia:polysilicon|polysilicon]] electrode. It used [[wikipedia:Aluminium|Al]] inter-connects and an [[wikipedia:Silicon|Si]] channels.
 
{{scrolling table/top|style=text-align: right; | first=Fab
 
{{scrolling table/top|style=text-align: right; | first=Fab
−
  |Type
+
  |Process Name
 +
|1st Production
 +
|Wafer
 +
|Metal Layers
 +
|&nbsp;
 
  |Contacted Gate Pitch
 
  |Contacted Gate Pitch
 
  |Interconnect Pitch (M1P)
 
  |Interconnect Pitch (M1P)
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{{scrolling table/mid}}
 
{{scrolling table/mid}}
 
|-
 
|-
−
! colspan="2" | [[Intel]]
+
! colspan="4" | [[Intel]] || colspan="2" | [[IBM]] || colspan="2" | [[AMD]] || colspan="2" | [[TI]] || colspan="2" | [[DEC]] || colspan="2" | [[IDT]] || colspan="2" | [[Fujitsu]] || colspan="2" | [[TSMC]] || colspan="2" | [[Samsung]] || colspan="2" | [[Toshiba]] || colspan="2" | [[Motorola]] || colspan="2" | [[NEC]]
 +
|- style="text-align: center;"
 +
| colspan="2" | P856 || colspan="2" | P856.5 || colspan="2" | CMOS-6X || colspan="2" | CS-44/CS44E/CS44E-Mod || colspan="2" | C07 || colspan="2" | CMOS-7 || colspan="2" | CMOS-10+ || colspan="2" | CS-70 || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" | HiPerMOS 4 || colspan="2" |
 +
|- style="text-align: center;"
 +
| colspan="2" | 1997 || colspan="2" | 1998 || colspan="2" | 1997  || colspan="2" | 1998 || colspan="2" | 1999 || colspan="2" | ? || colspan="2" | ? || colspan="2" | ? || colspan="2" | ? || colspan="2" | 1998 || colspan="2" | 1998 || colspan="2" | 1997 || colspan="2" |
 +
|- style="text-align: center;"
 +
| colspan="26" | 200 mm
 +
|- style="text-align: center;"
 +
| colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" | 4 || colspan="2" |  || colspan="2" |
 
|-
 
|-
−
! Value !! [[350 nm]] Δ
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! Value !! [[350 nm]] Δ !! Value !! 250 nm Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ
 
|-
 
|-
−
| ? nm || ?x
+
| 500 nm || 0.91x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || 640 nm || 0.8x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
 
|-
 
|-
−
| 608 nm || 0.69x
+
| 640 nm || 0.72x || ? nm || ?x || 700 nm || ?x || 880 nm || ?x || 850 nm || ?x || 840 nm || ?x || 940 nm || ?x || 900 nm || ?x || 640 nm || 0.67x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
 
|-
 
|-
−
| 10.26 µm<sup>2</sup> || 0.57x
+
| 10.26 µm² || 0.57x || 9.26 µm² || 0.90x || 8.6 µm² || ?x || ? µm² || ?x || 10.5 µm² || ?x || 11.5 µm² || ?x || 11.2 µm² || ?x || ? µm² || ?x || 7.56 µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || 12.77 µm² || ?x
 
{{scrolling table/end}}
 
{{scrolling table/end}}
 
=== Design Rules ===
 
=== Design Rules ===
−
 
 
{| class="wikitable collapsible collapsed"
 
{| class="wikitable collapsible collapsed"
 
|-
 
|-
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== 250 nm Microprocessors==
 
== 250 nm Microprocessors==
 +
* AMD
 +
** {{amd|K6}}
 +
** {{amd|K6-2}}
 +
** {{amd|K6-III}}
 +
** {{amd|Athlon}}
 +
* Centaur
 +
** {{centtech|WinChip 2B}}
 +
** {{centtech|WinChip 3}}
 +
* Cyrix
 +
** {{cyrix|MII}}
 +
* DEC
 +
** {{decc|Alpha 21264A}}
 +
* IBM
 +
** {{ibm|Power2}}
 +
** {{ibm|Power3}}
 +
** {{ibm|PowerPC 630}}
 +
** {{ibm|PowerPC 604ev}}
 
* Intel
 
* Intel
 
** {{intel|Pentium MMX}}, 200-300 MHz September, 1997
 
** {{intel|Pentium MMX}}, 200-300 MHz September, 1997
 
** {{intel|Pentium II}}, 333-450 MHz, January 1998
 
** {{intel|Pentium II}}, 333-450 MHz, January 1998
−
** {{intel|Pentium II}} Notebook, 233-300 MHz, April 1998
+
** {{intel|Mobile Pentium II}}, 233-300 MHz, April 1998
 +
** {{intel|Pentium II Xeon}}
 
** {{intel|Celeron}}, 200-300 MHz, April 1998
 
** {{intel|Celeron}}, 200-300 MHz, April 1998
 
** {{intel|Celeron}}, 300-533 MHz, August 1998
 
** {{intel|Celeron}}, 300-533 MHz, August 1998
 
** {{intel|Celeron}} Notebook, 266-466 MHz, January 1999
 
** {{intel|Celeron}} Notebook, 266-466 MHz, January 1999
 
** {{intel|Pentium III}}, 450-600 MHz, February 1999
 
** {{intel|Pentium III}}, 450-600 MHz, February 1999
 +
** {{intel|Pentium III Xeon}}
 
* MIPS
 
* MIPS
 
** {{mips|R10000}}, 1997, fab'ed by NEC
 
** {{mips|R10000}}, 1997, fab'ed by NEC
 +
* Qualcomm
 +
** {{qualcomm|MSM6xxx}}
 +
* Sun
 +
** {{sun|UltraSPARC II}}
 +
** {{sun|UltraSPARC IIi}}
 
{{expand list}}
 
{{expand list}}
  
 
== 250 nm Microarchitectures ==
 
== 250 nm Microarchitectures ==
 +
* AMD
 +
** {{amd|microarchitectures/K6|K6}}
 +
** {{amd|microarchitectures/K6-2|K6-2}}
 +
** {{amd|microarchitectures/K6-III|K6-III}}
 +
** {{amd|microarchitectures/K7|K7}}
 +
* ARM
 +
** {{armh|ARM7|l=arch}}
 +
* Intel
 +
** {{intel|P6}}
 
{{expand list}}
 
{{expand list}}
 +
 +
 +
== References ==
 +
* Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
 +
* Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998.
 +
* Seshan, Krishna, Timothy J. Maloney, and Kenneth J. Wu. "The quality and reliability of Intel's quarter micron process." (1998).
 +
* Thompson, Scott. "MOS scaling: Transistor challenges for the 21st century." Intel Technology Journal. 1998.
 +
 +
[[category:lithography]]

Latest revision as of 15:18, 21 August 2022

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 250 nanometer (250 nm) lithography process is a full node semiconductor manufacturing process following the 350 nm process node. Commercial integrated circuit manufacturing using 250 nm process began in 1997 and was eventually replaced by 180 nm by 1999.

Industry[edit]

The 0.25 µm-based process entered production at Intel in 1997. Intel original 0.25 micron process was named P856 or Process 856. A second process, named P856.5, was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm², 6T SRAM. The process used 200 mm wafers, SiO2 dielectric and polysilicon electrode. It used Al inter-connects and an Si channels.

Fab
Process Name​
1st Production​
Wafer​
Metal Layers​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Intel IBM AMD TI DEC IDT Fujitsu TSMC Samsung Toshiba Motorola NEC
P856 P856.5 CMOS-6X CS-44/CS44E/CS44E-Mod C07 CMOS-7 CMOS-10+ CS-70 HiPerMOS 4
1997 1998 1997 1998 1999  ?  ?  ?  ? 1998 1998 1997
200 mm
5 5 5 5 4
Value 350 nm Δ Value 250 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ
500 nm 0.91x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x 640 nm 0.8x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
640 nm 0.72x  ? nm  ?x 700 nm  ?x 880 nm  ?x 850 nm  ?x 840 nm  ?x 940 nm  ?x 900 nm  ?x 640 nm 0.67x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
10.26 µm² 0.57x 9.26 µm² 0.90x 8.6 µm²  ?x  ? µm²  ?x 10.5 µm²  ?x 11.5 µm²  ?x 11.2 µm²  ?x  ? µm²  ?x 7.56 µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x 12.77 µm²  ?x

Design Rules[edit]

250 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

250 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.


References[edit]

  • Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
  • Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998.
  • Seshan, Krishna, Timothy J. Maloney, and Kenneth J. Wu. "The quality and reliability of Intel's quarter micron process." (1998).
  • Thompson, Scott. "MOS scaling: Transistor challenges for the 21st century." Intel Technology Journal. 1998.
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