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{{lithography processes}}
 
{{lithography processes}}
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The '''350 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[500 nm lithography process|500 nm process]] node. Commercial [[integrated circuit]] manufacturing using 350 nm process began in late 1995. 350 nm was phased out and replaced by [[250 nm]] in 1999.
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The '''350 nanometer lithography process''' (350 nm or 0.35 µm) is a [[technology node|full node]] semiconductor manufacturing process following the [[500 nm lithography process|500 nm process]] node. Commercial [[integrated circuit]] manufacturing using 350 nm process began in late 1995. 350 nm was phased out and replaced by [[250 nm]] in 1999.
  
 
== Industry ==
 
== Industry ==
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  |Process Name
 
  |Process Name
 
  |1st Production
 
  |1st Production
 +
|Voltage
 
  |Metal Layers
 
  |Metal Layers
 
  | 
 
  | 
 +
|Gate Oxide
 
  |Contacted Gate Pitch
 
  |Contacted Gate Pitch
 
  |Interconnect Pitch (M1P)
 
  |Interconnect Pitch (M1P)
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{{scrolling table/mid}}
 
{{scrolling table/mid}}
 
|-
 
|-
−
! colspan="2" | [[Intel]] || colspan="2" | [[IBM]] || colspan="2" | [[AMD]] || colspan="2" | [[DEC]] || colspan="2" | [[Fujitsu]] || colspan="2" | [[IDT]] || colspan="2" | [[NEC]] || colspan="2" | [[TI]]
+
! colspan="2" | [[Intel]] || colspan="2" | [[IBM]] || colspan="2" | [[AMD]] || colspan="2" | [[AMD]] || colspan="2" | [[DEC]] || colspan="2" | [[Fujitsu]] || colspan="2" | [[IDT]] || colspan="2" | [[NEC]] || colspan="2" | [[TI]] || colspan="2" | [[Motorola]] || colspan="2" | [[Hitachi]] || [[Планар]] <ref>http://kb-omo.by/content/view/1080/599/</ref>
 
|- style="text-align: center;"
 
|- style="text-align: center;"
−
| colspan="2" | P854 || colspan="2" |  || colspan="2" | || colspan="2" | CMOS-6 || colspan="2" | CS-60 || colspan="2" |  || colspan="2" |  || colspan="2" |  
+
| colspan="2" | P854 || colspan="2" |  || colspan="2" | CS-34 || colspan="2" | CS-34EX || colspan="2" | CMOS-6 || colspan="2" | CS-60 || colspan="2" |  || colspan="2" |  || colspan="2" | || colspan="2" | HiPerMOS 2 || colspan="2" | || colspan="2" | КМОП 0,35
 
|- style="text-align: center;"
 
|- style="text-align: center;"
−
| colspan="2" | 1994 || colspan="2" | 1994 || colspan="2" | 1997 || colspan="2" | 1995 || colspan="2" | 1996 || colspan="2" | 1996 || colspan="2" | 1995 || colspan="2" | 1997
+
| colspan="2" | 1994 || colspan="2" | 1994 || colspan="2" | 1995 || colspan="2" |  || colspan="2" | 1995 || colspan="2" | 1996 || colspan="2" | 1996 || colspan="2" | 1995 || colspan="2" | 1997 || colspan="2" | 1996 || colspan="2" |  || colspan="2" |1997
 
|- style="text-align: center;"
 
|- style="text-align: center;"
−
| colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 6 || colspan="2" | 5 || colspan="2" | 3 || colspan="2" | 4 || colspan="2" | 5
+
| colspan="2" | 3.3 V || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" | 3,3V - 5V
 +
|- style="text-align: center;"
 +
| colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 3 || colspan="2" | 4 || colspan="2" | 5 || colspan="2" |  || colspan="2" |
 
|-
 
|-
−
! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ
+
! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[600 nm]] Δ
 
|-
 
|-
−
| 550 nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
+
| || || || || || || || || 6.5 nm || || || || || || || || || || || || || ||
 
|-
 
|-
−
| 880 nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
+
| 550 nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
 
|-
 
|-
−
| 18.1 µm<sup>2</sup> || 0.41x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x
+
| 880 nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || 750 nm || ?x
 +
|-
 +
| 18.1 µm² || 0.41x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || 21.67 µm² || ?x || ? µm² || ?x|| 18 µm² || ?x
 
{{scrolling table/end}}
 
{{scrolling table/end}}
−
=== Design Rules ===
+
=== Intel ===
 
{| class="wikitable collapsible collapsed"
 
{| class="wikitable collapsible collapsed"
 
|-
 
|-
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| Metal 4 || 1.70 µm || 1.70 µm  
 
| Metal 4 || 1.70 µm || 1.70 µm  
 
|}
 
|}
 +
=== DEC ===
 +
DEC's 0.35 µm process, called ''CMOS-6'', was designed at Fab-6 in Hudson, Mass. The process uses a Cobalt-Disilicide [[Salicide]] with L<sub>drawn</sub> of 0.35 µm with an L<sub>eff</sub> of 0.25 µm with a T<sub>ox</sub> of 6 nm. CMOS-6 was used for a number of DEC's processors such as Alpha and StrongARM. The plant was later sold to [[Intel]] where it continued to manufacture Intel's line of {{intel|XScale|l=arch}} processors.
  
 
== 350 nm Microprocessors==
 
== 350 nm Microprocessors==
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** {{intel|Mobile Pentium II}}
 
** {{intel|Mobile Pentium II}}
 
* AMD
 
* AMD
 +
** {{amd|Am5x86}}
 +
** {{amd|Am486#Enhanced Am486|Enhanced Am486}}
 +
** {{amd|K5}}
 
** {{amd|K6}}
 
** {{amd|K6}}
 
* DEC
 
* DEC
 
** {{decc|Alpha 21164A}}
 
** {{decc|Alpha 21164A}}
 
** {{decc|Alpha 21264}}
 
** {{decc|Alpha 21264}}
 +
** {{decc|StrongARM}}
 
* HAL
 
* HAL
 
** {{hal|SPARC64 II}}
 
** {{hal|SPARC64 II}}
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* Cyrix
 
* Cyrix
 
** {{Cyrix|6x86}}
 
** {{Cyrix|6x86}}
−
* MIPs
+
* MIPS
 
** {{mips|R5000}}
 
** {{mips|R5000}}
 
** {{mips|R10000}}
 
** {{mips|R10000}}
 
** {{mips|R4400}}
 
** {{mips|R4400}}
−
** Sun
+
* Sun
 
** {{sun|UltraSPARC II}}
 
** {{sun|UltraSPARC II}}
 
** {{sun|UltraSPARC IIi}}
 
** {{sun|UltraSPARC IIi}}
 +
* NEC
 +
** {{nec|VR4300}}
 +
* Parallax
 +
** {{parallax|Propeller 1}}
 +
{{expand list}}
 +
 +
== 350 nm Microcontrollers==
 +
* AMD
 +
** {{amd|Am186Cx}}
 +
** {{amd|Am186Ex}}
 
{{expand list}}
 
{{expand list}}
  
 
== 350 nm Microarchitectures ==
 
== 350 nm Microarchitectures ==
 +
* AMD
 +
** {{amd|K5|l=arch}}
 +
** {{amd|K6|l=arch}}
 +
* Intel
 +
** {{intel|80186|l=arch}} (embedded [[IP cores]] only)
 +
* DEC
 +
** {{decc|Alpha 21264|l=arch}}
 +
** {{decc|StrongARM|l=arch}}
 
{{expand list}}
 
{{expand list}}
 +
 +
== 350 nm Mikron ==
 +
* МЦСТ <ref>http://www.mcst.ru/chips</ref>
 +
** МЦСТ-R150
 +
 +
== References ==
 +
* Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
 +
* von Kaenel, Vincent, et al. "A 320 MHz, 1.5 mW@ 1.35 V CMOS PLL for microprocessor clock generation." IEEE Journal of Solid-State Circuits 31.11 (1996): 1715-1722.
 +
 +
[[category:lithography]]

Latest revision as of 21:44, 4 April 2022

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 350 nanometer lithography process (350 nm or 0.35 µm) is a full node semiconductor manufacturing process following the 500 nm process node. Commercial integrated circuit manufacturing using 350 nm process began in late 1995. 350 nm was phased out and replaced by 250 nm in 1999.

Industry[edit]

Fab
Process Name​
1st Production​
Voltage​
Metal Layers​
 ​
Gate Oxide​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Intel IBM AMD AMD DEC Fujitsu IDT NEC TI Motorola Hitachi Планар [1]
P854 CS-34 CS-34EX CMOS-6 CS-60 HiPerMOS 2 КМОП 0,35
1994 1994 1995 1995 1996 1996 1995 1997 1996 1997
3.3 V 3,3V - 5V
4 5 5 5 4 5 3 4 5
Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 600 nm Δ
6.5 nm
550 nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
880 nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x 750 nm  ?x
18.1 µm² 0.41x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x 21.67 µm²  ?x  ? µm²  ?x 18 µm²  ?x

Intel[edit]

DEC[edit]

DEC's 0.35 µm process, called CMOS-6, was designed at Fab-6 in Hudson, Mass. The process uses a Cobalt-Disilicide Salicide with Ldrawn of 0.35 µm with an Leff of 0.25 µm with a Tox of 6 nm. CMOS-6 was used for a number of DEC's processors such as Alpha and StrongARM. The plant was later sold to Intel where it continued to manufacture Intel's line of XScale processors.

350 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

350 nm Microcontrollers[edit]

This list is incomplete; you can help by expanding it.

350 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

350 nm Mikron[edit]

  • МЦСТ [2]
    • МЦСТ-R150

References[edit]

  • Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
  • von Kaenel, Vincent, et al. "A 320 MHz, 1.5 mW@ 1.35 V CMOS PLL for microprocessor clock generation." IEEE Journal of Solid-State Circuits 31.11 (1996): 1715-1722.
  • ↑ http://kb-omo.by/content/view/1080/599/
  • ↑ http://www.mcst.ru/chips
    • Retrieved from "https://en.wikichip.org/w/index.php?title=350_nm_lithography_process&oldid=99922"