From WikiChip
Difference between revisions of "2 µm lithography process"
(2 intermediate revisions by 2 users not shown) | |||
Line 264: | Line 264: | ||
| fab 10 dram.edram = | | fab 10 dram.edram = | ||
| fab 10 dram.edramΔ = | | fab 10 dram.edramΔ = | ||
+ | |||
+ | | fab 11 name link = sanyo | ||
+ | | fab 11 name = Sanyo | ||
+ | | fab 11 proc name = | ||
+ | | fab 11 date = | ||
+ | | fab 11 wafer.type = Bulk | ||
+ | | fab 11 wafer.size = | ||
+ | | fab 11 xtor.tech = | ||
+ | | fab 11 xtor.type = | ||
+ | | fab 11 xtor.volt = | ||
+ | | fab 11 layers = | ||
+ | | fab 11 diff from = | ||
+ | | fab 11 xtor.lg = | ||
+ | | fab 11 xtor.lgΔ = | ||
+ | | fab 11 xtor.cpp = | ||
+ | | fab 11 xtor.cppΔ = | ||
+ | | fab 11 xtor.mmp = | ||
+ | | fab 11 xtor.mmpΔ = | ||
+ | | fab 11 sram.hp = | ||
+ | | fab 11 sram.hpΔ = | ||
+ | | fab 11 sram.hd = | ||
+ | | fab 11 sram.hdΔ = | ||
+ | | fab 11 sram.lv = | ||
+ | | fab 11 sram.lvΔ = | ||
+ | | fab 11 dram.edram = | ||
+ | | fab 11 dram.edramΔ = | ||
}} | }} | ||
Line 278: | Line 304: | ||
** {{amd|Am29100}} | ** {{amd|Am29100}} | ||
** {{amd|Am29500}} | ** {{amd|Am29500}} | ||
+ | * Intel | ||
+ | ** [[/Intel/8031AH|8031AH]] | ||
+ | ** [[/Intel/8031AH|8033AH]] | ||
+ | ** [[/Intel/8031AH|8051AH]] | ||
+ | ** [[/Intel/8031AH|8052AH]] | ||
{{expand list}} | {{expand list}} | ||
Line 288: | Line 319: | ||
* Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984. | * Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984. | ||
− | [[ | + | [[category:lithography]] |
Latest revision as of 11:31, 22 February 2019
The 2 µm lithography process was the semiconductor process technology used by the some semiconductor companies in the mid to late 1980s. By the mid 80s this process was replaced by 1.5 µm, 1.3 µm, and 1.2 µm processes.
Industry[edit]
Foundry | |
---|---|
Process Name | |
1st Production | |
Wafer | Type |
Size | |
Transistor | Technology |
Type | |
Voltage | |
Metal Layers | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Intel | Intel | Intel | AMD | Motorola | STMicro | Toshiba | TI | Hitachi | VLSI Technology | Sanyo | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHMOS II | P414.1 (HMOS-II) | P421.X (HMOS-E) | Hi-CMOS II | ||||||||||||||||||
1979 | 1980 | 1980 | 1992 | 1982 | |||||||||||||||||
Bulk | Bulk | Bulk | Bulk | Bulk | Bulk | Bulk | Bulk | Bulk | Bulk | ||||||||||||
CMOS | pMOS | ||||||||||||||||||||
Planar | Planar | Planar | |||||||||||||||||||
5 V | 5 V | 5 V | 5 V | ||||||||||||||||||
1 | |||||||||||||||||||||
Value | 3 µm Δ | Value | Value | N/A | Value | N/A | Value | N/A | Value | N/A | Value | N/A | Value | N/A | Value | 3 µm | Value | Value | |||
2 µm | 0.80x | 2 µm | 0.67x | ||||||||||||||||||
5.6 µm | |||||||||||||||||||||
8 µm | 3 µm | 1.00x | |||||||||||||||||||
1740 µm² | 303.8 µm² | 0.34x | |||||||||||||||||||
Microprocessors[edit]
This list is incomplete; you can help by expanding it.
Microarchitectures[edit]
- ARM
References[edit]
- Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
- Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.