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	| process 1 fab          = [[TSMC]]		| process 1 fab          = [[TSMC]]
−	| process 1 name        = 16FF, 16FF+, 12FFN	+	| process 1 name        = 16FF<info>16nm FinFET</info>, 16FF+<info>16nm FinFET Plus</info>, 16FFC, 12FFC<info>12nm FinFET Compact</info>, 12FFN
	| process 1 date        = 3Q 2015		| process 1 date        = 3Q 2015
	| process 1 lith        = 193 nm		| process 1 lith        = 193 nm

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Revision as of 14:48, 24 September 2017

The 16 nanometer (16 nm) lithography process is a full node semiconductor manufacturing process following the 20 nm process stopgap. Commercial integrated circuit manufacturing using 16 nm process began in 2014. The term "16 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with 10 nm process in 2017.

Industry

An enhanced version of TSMC's 16nm process was introduced in late 2016 called "12nm".

Process Name
1st Production
Lithography	Lithography
	Immersion
	Exposure
Wafer	Type
	Size
Transistor	Type
	Voltage
Fin	Pitch
	Width
	Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell	High-Perf (HP)
	High-Density (HD)
	Low-Voltage (LV)
DRAM bitcell	eDRAM

TSMC

TSMC uses the same BEOL as its 20nm process. They named their process 16 nm which reflects those relaxed pitches. TSMC demonstrated their 128 Mebibit SRAM wafer from their 16 nm HKMG FinFET process at the 2014 IEEE ISSCC. TSMC followed their 16FF process by the 16FF+ which provided roughly 10-15% performance improvement. A final 16FFC (16FF Compact) designed to reduce cost through less masks while using half the power.

In late 2016 TSMC introduced a "12nm" process (e.g. 12FFC

12nm FinFET Compact Technology

) which uses the same design rules as the 16nm node. A modest density increase might be observed from more optimized cells. The enhanced process is said to feature lower leakage better and cost characteristics and perhaps a better name (vs. "14nm"). 12nm is expected to enter mass production in late 2017.

TSMC 128 Mib SRAM demo 16 nm wafer
Technology 16 nm HK-MG FinFET Metal scheme 1 Poly / 7 Metal Supply voltage 0.85 V (core) 1.8 V (i/o) Bit cell size 0.07 µm² macro configs 4096x32 MUX16 258 bits/BL 272 bits/WL Capacity 128 Mib Test Features Row/Column Redundancy Programmable E-fuse Die Size 42.6 mm²

16 nm Microprocessors

• HiSilicon
  • Kirin
• PEZY
  • PEZY-SC2
• MediaTek
  • Helio
• Microsoft
  • Scorpio Engine
• Renesas
  • R-Car

This list is incomplete; you can help by expanding it.

16 nm Microarchitectures

• ARM
  • Cortex-A55

This list is incomplete; you can help by expanding it.

References

• Chen, Yen-Huei, et al. "A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 170-177.
• Wu, Shien-Yang, et al. "A 16nm FinFET CMOS technology for mobile SoC and computing applications." Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE, 2013.
• TechInsights/Chipworks, Kevin Gibb, The ConFab 2016