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Difference between revisions of "2 µm lithography process"
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+ | | fab 10 name = VLSI Technology | ||
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+ | | fab 10 wafer.type = Bulk | ||
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+ | | fab 10 xtor.lg = | ||
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+ | | fab 10 xtor.mmp = | ||
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+ | | fab 10 sram.hd = | ||
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+ | | fab 10 sram.lv = | ||
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Revision as of 23:00, 27 June 2017
The 2 µm lithography process was the semiconductor process technology used by the some semiconductor companies in the mid to late 1980s. By the mid 80s this process was replaced by 1.5 µm, 1.3 µm, and 1.2 µm processes.
Industry
Foundry | |
---|---|
Process Name | |
1st Production | |
Wafer | Type |
Size | |
Transistor | Technology |
Type | |
Voltage | |
Metal Layers | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Intel | Intel | Intel | AMD | Motorola | STMicro | Toshiba | TI | Hitachi | VLSI Technology | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHMOS II | P414.1 (HMOS-II) | P421.X (HMOS-E) | Hi-CMOS II | ||||||||||||||||
1979 | 1980 | 1980 | 1992 | 1982 | |||||||||||||||
Bulk | Bulk | Bulk | Bulk | Bulk | Bulk | Bulk | Bulk | Bulk | |||||||||||
CMOS | pMOS | ||||||||||||||||||
Planar | Planar | Planar | |||||||||||||||||
5 V | 5 V | 5 V | 5 V | ||||||||||||||||
1 | |||||||||||||||||||
Value | 3 µm Δ | Value | Value | N/A | Value | N/A | Value | N/A | Value | N/A | Value | N/A | Value | N/A | Value | 3 µm | Value | ||
2 µm | 0.80x | 2 µm | 0.67x | ||||||||||||||||
5.6 µm | |||||||||||||||||||
8 µm | 3 µm | 1.00x | |||||||||||||||||
1740 µm² | 303.8 µm² | 0.34x | |||||||||||||||||
Microprocessors
This list is incomplete; you can help by expanding it.
References
- Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
- Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.