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Difference between revisions of "1.5 µm lithography process"
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== 1.5 µm Microarchitectures == | == 1.5 µm Microarchitectures == | ||
* Intel | * Intel | ||
− | ** {{intel| | + | ** {{intel|80386|l=arch}} |
{{expand list}} | {{expand list}} | ||
+ | * DEC | ||
+ | ** {{decc|MicroPrism|l=arch}} | ||
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[[Category:Lithography]] | [[Category:Lithography]] |
Revision as of 13:44, 11 June 2017
The 1.5 µm lithography process was the semiconductor process technology used by the major semiconductor companies in the mid 1980s. This process had an effective channel length of roughly 1.5 µm between the source and drain. By the late 80s this process was replaced by 1.3 µm, 1.2 µm, and 1 µm processes.
Industry
Fab |
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Process Name |
1st Production |
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
Metal Layers |
SRAM bit cell |
Wafer |
Intel | Intel | Intel | HP | AMD |
---|---|---|---|---|
HMOS-II | HMOS-E | P646 (CHMOS III) | NMOS III | |
1982 | 1982 | 1985 | 1981 | 1982 |
? nm | ? nm | ? nm | 1.5 µm | |
? nm | ? nm | ? nm | 2.5 µm | |
2 | ? | 2 | 2 | 2 |
? µm2 | ? µm2 | ? µm2 | ? µm2 | ? µm2 |
125 mm | 150 mm |
Design Rules
[show] HP NMOS-III Design Rules |
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1.5 µm Microprocessors
This list is incomplete; you can help by expanding it.
1.5 µm Microarchitectures
- Intel
This list is incomplete; you can help by expanding it.
- DEC