Semiconductor & Computer Engineering
(→Industry) |
|||
| Line 82: | Line 82: | ||
| process 3 wafer type = Bulk | | process 3 wafer type = Bulk | ||
| process 3 wafer size = 300 nm | | process 3 wafer size = 300 nm | ||
| − | | process 3 transistor = | + | | process 3 transistor = |
| process 3 volt = | | process 3 volt = | ||
| process 3 delta from = [[7 nm]] Δ | | process 3 delta from = [[7 nm]] Δ | ||
| Line 137: | Line 137: | ||
| process 4 dram = | | process 4 dram = | ||
| process 4 dram Δ = | | process 4 dram Δ = | ||
| + | |||
| + | <!-- Common Platform --> | ||
| + | | process 5 fab = Common Platform<info>[[IBM]], [[Samsung]], [[GlobalFoundries]]</info> Paper | ||
| + | | process 5 name = | ||
| + | | process 5 date = | ||
| + | | process 5 lith = EUV | ||
| + | | process 5 immersion = | ||
| + | | process 5 exposure = SE | ||
| + | | process 5 wafer type = Bulk | ||
| + | | process 5 wafer size = 300 nm | ||
| + | | process 5 transistor = GAA | ||
| + | | process 5 volt = | ||
| + | | process 5 delta from = [[7 nm]] Δ | ||
| + | | process 5 fin pitch = - | ||
| + | | process 5 fin pitch Δ = | ||
| + | | process 5 fin width = | ||
| + | | process 5 fin width Δ = | ||
| + | | process 5 fin height = | ||
| + | | process 5 fin height Δ = | ||
| + | | process 5 gate len = 12 nm | ||
| + | | process 5 gate len Δ = | ||
| + | | process 5 cpp = 48 nm | ||
| + | | process 5 cpp Δ = 1.00x | ||
| + | | process 5 mmp = | ||
| + | | process 5 mmp Δ = | ||
| + | | process 5 sram hp = | ||
| + | | process 5 sram hp Δ = | ||
| + | | process 5 sram hd = | ||
| + | | process 5 sram hd Δ = | ||
| + | | process 5 sram lv = | ||
| + | | process 5 sram lv Δ = | ||
| + | | process 5 dram = | ||
| + | | process 5 dram Δ = | ||
}} | }} | ||
=== Intel === | === Intel === | ||
In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in development phase. | In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in development phase. | ||
| + | |||
| + | === Common Platform Alliance Paper === | ||
| + | In a joint paper by the [[Common Platform]] (IBM, GlobalFoundries, Samsung) a 5nm node was proposed at the 2017 VLSI Symposium. The paper presents a new horizontally stacked nanowires [[gate-all-around]] (GAA) FET with good properties which can be a good candidate for the replacement of FinFET at the 5nm node. The paper reports transistors with an aggressive L<sub>g</sub> of 12 nm and a contacted poly pitch of 48 nm. | ||
| + | |||
| + | [[File:ibm stacked silicon nanowire transistors.jpg|400px]] | ||
== 5 nm Microprocessors== | == 5 nm Microprocessors== | ||
Revision as of 09:15, 5 June 2017
Semiconductor lithography processes technology
The 5 nanometer (5 nm or 50 Å) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2020.
The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.
Contents
Industry
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Intel | TSMC | GlobalFoundries | Samsung | Common Platform Paper | |||||
|---|---|---|---|---|---|---|---|---|---|
| P1278? (CPU), P1279? (SoC) | |||||||||
| 193 nm | EUV | EUV | EUV | ||||||
| Yes | Yes | ||||||||
| LELELELE | SE | SE | SE | ||||||
| Bulk | Bulk | Bulk | Bulk | Bulk | |||||
| 300 nm | 300 nm | 300 nm | 300 nm | 300 nm | |||||
| FinFET | FinFET | GAA | |||||||
| Value | 7 nm Δ | Value | 7 nm Δ | Value | 7 nm Δ | Value | 7 nm Δ | Value | 7 nm Δ |
| N/A | |||||||||
| 12 nm | |||||||||
| ~44 nm | 0.81x | 48 nm | 1.00x | ||||||
| ~32 nm | 0.84x | ||||||||
Intel
In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in development phase.
Common Platform Alliance Paper
In a joint paper by the Common Platform (IBM, GlobalFoundries, Samsung) a 5nm node was proposed at the 2017 VLSI Symposium. The paper presents a new horizontally stacked nanowires gate-all-around (GAA) FET with good properties which can be a good candidate for the replacement of FinFET at the 5nm node. The paper reports transistors with an aggressive Lg of 12 nm and a contacted poly pitch of 48 nm.
5 nm Microprocessors
This list is incomplete; you can help by expanding it.
5 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017