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Difference between revisions of "10 nm lithography process"
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Revision as of 11:21, 24 December 2016
The 10 nanometer (10 nm) lithography process is a full node semiconductor manufacturing process following the 14 nm process stopgap. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial mass production of integrated circuit manufacturing using 10 nm process begun in late 2016. This technology is set to be replaced by 7 nm process 2019.
Industry
Fab |
---|
Process Name |
1st Production |
|
Fin Pitch |
Fin Width |
Fin Height |
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell (HP) |
SRAM bit cell (HD) |
Intel | Samsung | TSMC | |||
---|---|---|---|---|---|
P1274 | 10LPE 1st generation; 10 nm Low Power Early , 10LPP2nd generation; 10 nm Low Power Performance , 10LPU3rd generation; 10 nm Low Power Ultimate |
||||
2017 | 2016 | 2017 | |||
Value | 14 nm Δ | Value | 14 nm Δ | Value | 16 nm Δ |
? nm | ?x | ? nm | ?x | ? nm | ?x |
? nm | ?x | ? nm | ?x | ? nm | ?x |
? nm | ?x | ? nm | ?x | ? nm | ?x |
54 nm[1] | 0.77x | ? nm | ?x | ? nm | ?x |
? nm | ?x | ? nm | ?x | ? nm | ?x |
? µm² | ?x | 0.049 µm²[2] | 0.61x | ? µm² | ?x |
? µm² | ?x | 0.040 µm²[3] | 0.63x | ? µm² | ?x |
10 nm Microprocessors
- MediaTek
- Qualcomm
This list is incomplete; you can help by expanding it.
10 nm Microarchitectures
- Intel
- Qualcomm
This list is incomplete; you can help by expanding it.
References
- ↑ Based on a presentation by Mark Bohr, Intel
- ↑ Samsung, IEEE International Solid-State Circuits Conference (ISSCC) 2016
- ↑ Samsung, IEEE International Solid-State Circuits Conference (ISSCC) 2016