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Difference between revisions of "32 nm lithography process"

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=== Toshiba / NEC ===
 
=== Toshiba / NEC ===

Revision as of 23:19, 23 April 2016

basic wafer drawing.svg Semiconductor lithography processes technology
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The 32 nm lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.

Industry

Intel

Measurement Scaling from 45 nm
Contacted Gate Pitch 112.5 nm 0.63x
Interconnect Pitch (M1P) 112.5 nm 0.70x
SRAM bit cell 0.171 µm2 0.63x
Design Rules
Layer Pitch Thick Aspect Ratio
Isolation 140 nm 200 -
Contacted Gate 112.5 nm 35 nm --
Metal 1 112.5 nm 95 nm 1.7
Metal 2 112.5 nm 95 nm 1.7
Metal 3 112.5 nm 95 nm 1.7
Metal 4 168.8 nm 151 nm 1.8
Metal 5 225.0 nm 204 nm 1.8
Metal 6 337.6 nm 303 nm 1.8
Metal 7 450.1 nm 388 nm 1.7
Metal 8 566.5 nm 504 nm 1.8
Metal 9 19.4 µm 8 µm 1.5

Samsung

Measurement
Contacted Gate Pitch 113.4 nm
Interconnect Pitch (M1P) 113.4 nm
SRAM bit cell 0.120 µm2

TSMC

In 2010, TSMC cancelled its 32nm node process.

Measurement
Contacted Gate Pitch 130 nm
Interconnect Pitch (M1P)  ? nm
SRAM bit cell 0.15 µm2

Toshiba / NEC

Measurement
Contacted Gate Pitch 120 nm
Interconnect Pitch (M1P)  ? nm
SRAM bit cell 0.124 µm2

32 nm Microprocessors

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32 nm System on Chips

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32 nm Microarchitectures

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