The 20 nanometer (20 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 22 nm and 16 nm processes. The term "20 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 20 nm process began in 2014. This technology superseded by commercial 16 nm process.

Industry

Process Name
1st Production
Lithography	Lithography
	Immersion
	Exposure
Wafer	Type
	Size
Transistor	Type
	Voltage
Metal Layers
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell	High-Perf (HP)
	High-Density (HD)
	Low-Voltage (LV)
DRAM bitcell	eDRAM

TSMC		Common Platform Alliance The Common Platform Alliance 20 nm node was a collaboration between IBM, Samsung, GlobalFoundries, Toshiba, STMicroelectronics
3Q 2014		2014
193 nm		193 nm
Yes		Yes
Bulk		Bulk
300 mm		300 mm
Planar		Planar
0.95 V		0.9 V
10
Value	28 nm Δ	Value	28 nm Δ
		20 nm	0.67x
90 nm	0.77x	86 nm	0.76
64 nm	0.67x	64 nm	0.71x
		0.102 µm²
0.081 µm²	0.64x	0.081 µm²	0.68x

TSMC

TSMC demonstrated their 112 Mebibit SRAM wafer from their 20 nm HKMG process at the 2013 IEEE ISSCC.

TSMC 112 Mib SRAM demo 20 nm wafer
Technology 20 nm HK-MG Metal scheme 1 Poly / 7 Metal Supply voltage 0.95 V (core) 1.8 V (i/o) Bit cell size 0.081 µm² macro configs 2048x134 MUX4 Capacity 112 Mib Test Features Row/Column Redundancy Programmable E-fuse Die Size 6400 µm x 6300 µm = 40.32 mm²

20 nm Microprocessors

• MediaTek
  • Helio
• Fujitsu
  • SPARC64
• Oracle
  • SPARC M8

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20 nm Microarchitectures

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References

• Chang, Jonathan, et al. "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-V MIN applications." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. IEEE, 2013.
• Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.