Difference between revisions of "32 nm lithography process"

Revision as of 03:15, 24 April 2016

Semiconductor lithography processes technology

The 32 nm lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.

Industry

TSMC cancelled its planned 32nm node process.

Fab
Type

Contacted Gate Pitch
Interconnect Pitch (M1P)
SRAM bit cell

Common Platform IBM, Freescale, AMD		Intel		TSMC		Samsung		Toshiba / NEC		Common Platform 2 IBM, STMicroelectronics, Frescale, Chartered, Infineon
PDSOI		Bulk
Value	45 nm Δ	Value	45 nm Δ	Value	45 nm Δ	Value	45 nm Δ	Value	45 nm Δ	Value	45 nm Δ
130 nm	0.68x	112.5 nm	0.63x	130 nm	0.80x	113.4 nm	?x	120 nm	?x	126 nm	?x
? nm	?x	112.5 nm	0.70x	? nm	?x	113.4 nm	?x	? nm	?x	?nm	?x
0.15 µm²	0.41	0.171 µm²	0.63x	0.15 µm²	0.62x	0.120 µm²	?x	0.124 µm²	?x	0.157 µm²	?x

Design Rules

Intel 32nm Design Rules
Layer	Pitch	Thick	Aspect Ratio
Isolation	140 nm	200	-
Contacted Gate	112.5 nm	35 nm	--
Metal 1	112.5 nm	95 nm	1.7
Metal 2	112.5 nm	95 nm	1.7
Metal 3	112.5 nm	95 nm	1.7
Metal 4	168.8 nm	151 nm	1.8
Metal 5	225.0 nm	204 nm	1.8
Metal 6	337.6 nm	303 nm	1.8
Metal 7	450.1 nm	388 nm	1.7
Metal 8	566.5 nm	504 nm	1.8
Metal 9	19.4 µm	8 µm	1.5

32 nm Microprocessors

AMD
- A8
- A10
Intel
- Core i7EE

This list is incomplete; you can help by expanding it.

32 nm System on Chips

This list is incomplete; you can help by expanding it.

32 nm Microarchitectures

Intel:

This list is incomplete; you can help by expanding it.

@@ Line 3: / Line 3: @@
 == Industry ==
+TSMC cancelled its planned 32nm node process.
-=== Intel ===
+{{scrolling table/top|style=text-align: right; | first=Fab
-{| class="wikitable"
+ |Type
+ |&nbsp;
+ |Contacted Gate Pitch
+ |Interconnect Pitch (M1P)
+ |SRAM bit cell
+}}
+{{scrolling table/mid}}
 |-
-| || Measurement || Scaling from [[45 nm]]
+! colspan="2" | Common Platform <info>[[IBM]], [[Freescale]], [[AMD]]</info> !! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Toshiba]] / NEC !! colspan="2" | Common Platform 2<info>[[IBM]], [[STMicroelectronics]], [[Frescale]], [[Chartered]], [[Infineon]]</info>
 |-
-| Contacted Gate Pitch || 112.5 nm || 0.63x
+| colspan="2" | PDSOI || colspan="10" | Bulk
 |-
-| Interconnect Pitch (M1P) || 112.5 nm || 0.70x
+! Value !! [[45 nm]] Δ !! Value !! [[45 nm]] Δ !! Value !! [[45 nm]] Δ || Value !! [[45 nm]] Δ || Value !! [[45 nm]] Δ || Value !! [[45 nm]] Δ
 |-
-| [[SRAM]] bit cell || 0.171 µm<sup>2</sup> || 0.63x
+| 130 nm || 0.68x || 112.5 nm || 0.63x || 130 nm || 0.80x || 113.4 nm || ?x || 120 nm || ?x || 126 nm || ?x
-|}
-{| class="wikitable"
 |-
-! colspan="4" | Design Rules
+| ? nm || ?x || 112.5 nm || 0.70x || ? nm || ?x || 113.4 nm || ?x || ? nm || ?x || ?nm || ?x
+|-
+| 0.15 µm<sup>2</sup> || 0.41 || 0.171 µm<sup>2</sup> || 0.63x || 0.15 µm<sup>2</sup> || 0.62x || 0.120 µm<sup>2</sup> || ?x || 0.124 µm<sup>2</sup> || ?x || 0.157 µm<sup>2</sup> || ?x
+{{scrolling table/end}}
+=== Design Rules ===
+{| class="wikitable collapsible collapsed"
+|-
+! colspan="4" | Intel 32nm Design Rules
 |-
 ! Layer !! Pitch !! Thick !! Aspect Ratio
@@ Line 43: / Line 53: @@
 |-
 | Metal 9 || 19.4 µm || 8 µm || 1.5
-|}
-=== Samsung ===
-{| class="wikitable"
-|-
-| || Measurement
-|-
-| Contacted Gate Pitch || 113.4 nm
-|-
-| Interconnect Pitch (M1P) || 113.4 nm
-|-
-| [[SRAM]] bit cell || 0.120 µm<sup>2</sup>
-|}
-=== TSMC ===
-In 2010, TSMC cancelled its 32nm node process.
-{| class="wikitable"
-|-
-| || Measurement
-|-
-| Contacted Gate Pitch || 130 nm
-|-
-| Interconnect Pitch (M1P) || ? nm
-|-
-| [[SRAM]] bit cell || 0.15 µm<sup>2</sup>
-|}
-=== Toshiba / NEC ===
-{| class="wikitable"
-|-
-| || Measurement
-|-
-| Contacted Gate Pitch || 120 nm
-|-
-| Interconnect Pitch (M1P) || ? nm
-|-
-| [[SRAM]] bit cell || 0.124 µm<sup>2</sup>
 |}

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Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Revision as of 03:15, 24 April 2016

Contents

Industry

Design Rules

32 nm Microprocessors

32 nm System on Chips

32 nm Microarchitectures