The 20 nanometer (20 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 22 nm and 16 nm processes. The term "20 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 20 nm process began in 2014. This technology superseded by commercial 16 nm process.

Industry

Fab
Process Name​
Transistor​
Wafer​
​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell

Samsung		TSMC
20LPM
Planar
300 mm
Value	28 nm Δ	Value	28 nm Δ
86 nm	0.75x	87 nm	0.71x
64 nm	0.71x	67 nm	0.70x
0.081 µm²	0.675x	0.081 µm²	0.64x

TSMC

TSMC demonstrated their 112 Mebibit SRAM wafer from their 20 nm HKMG process at the 2013 IEEE ISSCC.

TSMC 112 Mib SRAM demo 20 nm wafer
Technology 20 nm HK-MG Metal scheme 1 Poly / 7 Metal Supply voltage 0.95 V (core) 1.8 V (i/o) Bit cell size 0.081 µm² macro configs 2048x134 MUX4 Capacity 112 Mib Test Features Row/Column Redundancy Programmable E-fuse Die Size 6400 µm x 6300 µm = 40.32 mm²

References

• Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.

20 nm Microprocessors

• MediaTek
  • Helio

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20 nm Microarchitectures

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References

• Chang, Jonathan, et al. "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-V MIN applications." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. IEEE, 2013.