The 1.5 µm lithography process was the semiconductor process technology used by the major semiconductor companies in the mid 1980s. This process had an effective channel length of roughly 1.5 µm between the source and drain. By the late 80s this process was replaced by 1.3 µm, 1.2 µm, and 1 µm processes.

Industry

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
Metal Layers​​
SRAM bit cell​
Wafer

Intel	Intel	Intel	HP	AMD	DEC
HMOS-II	HMOS-E	P646 (CHMOS III)	NMOS III		CMOS-2
1982	1982	1985	1981	1982
? nm	? nm	? nm	1.5 µm
? nm	? nm	? nm	2.5 µm
2	?	2	2	2	2
? µm²	? µm²	? µm²	? µm²	? µm²
125 mm		150 mm

HP

HP NMOS-III Design Rules
Layer	Description
Oxide	450 nm thick silicon dioxide 1.5 µm x 1.5 µm minimum contact area, zero overlap to polysilicon, zero overlap of first metal layer
M1	1.5 µm wide line / 1.0 µm space 0.4 ohm/square sheet resistance
Intemediate Oxide	550 nm-thick silicon dioxide 1.5 µm x 2.0 µm minimum contact area, zero overlap to first metal layer 2.0 µm overlap of second metal layer to via
M2	5.0 µm wide line / 3.0 µm space 0.4 ohm/square sheet resistance

DEC

DEC operated their 1.5 µm process (CMOS-2) at their Hudson foundry. This 2 ML process had an effective channel length of 0.9 µm with a polycide width of 1.5 µm (1.5 µm spacing) and a T_OX of 22.5 nm.

DEC Design Rules
	Width	Spacing
Polycide	1.5 µm	1.5 µm
Metal 1	3 µm	1.5 µm
Metal 1 Contact	1.5 µm x 1.5 µm
Metal 2	3.75 µm	1.5
Metal 2 Contact	1.5 µm x 1.5 µm

1.5 µm Microprocessors

• AMD
  • Am186
  • Am286
• Intel
  • 80286
  • 80386 DX
  • 80387
• HP
  • FOCUS
• Dec
  • Rigel

This list is incomplete; you can help by expanding it.

1.5 µm Microarchitectures

• Intel
  • 80386

This list is incomplete; you can help by expanding it.

• DEC
  • MicroPrism
  • MicroTitan