The 16 nanometer (16 nm) lithography process is a full node semiconductor manufacturing process following the 20 nm process stopgap. Commercial integrated circuit manufacturing using 16 nm process began in 2014. The term "16 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with 10 nm process in 2017.

Industry

Fab
Wafer​
​
Fin Pitch​
Fin Width​
Fin Height​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell

TSMC
300mm
Value	20 nm Δ
48 nm	N/A
? nm
37 nm
90 nm	1.03x
70 nm	1.09x
0.07 µm²	0.55x

TSMC

TSMC demonstrated their 256 Mebibit SRAM wafer from their 7nm HKMG FinFET process. Their chip makes use of 34% of the area of their 16 nm process demo chip counterpart.

TSMC 256Mb SRAM demo wafer
Technology 16 nm HK-MG FinFET Metal scheme 1P7M Supply voltage 0.85 V (core) 1.8 V (i/o) Bit cell size 0.07 µm² macro configs 4096x32 MUX16 258 bits/BL 272 bits/WL Capacity 256 Mib Test Features Row/Column Redundancy Programmable E-fuse Die Size 42.6 mm²

16 nm Microprocessors

• PEZY
  • PEZY-SC2
• MediaTek
  • Helio

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16 nm Microarchitectures

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