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32 nm lithography process
Revision as of 02:15, 24 April 2016 by David (talk | contribs) (Industry)

The 32 nm lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.

Industry

TSMC cancelled its planned 32nm node process.

Fab
Type​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Common Platform Intel TSMC Samsung Toshiba / NEC Common Platform 2
PDSOI Bulk
Value 45 nm Δ Value 45 nm Δ Value 45 nm Δ Value 45 nm Δ Value 45 nm Δ Value 45 nm Δ
130 nm 0.68x 112.5 nm 0.63x 130 nm 0.80x 113.4 nm  ?x 120 nm  ?x 126 nm  ?x
 ? nm  ?x 112.5 nm 0.70x  ? nm  ?x 113.4 nm  ?x  ? nm  ?x  ?nm  ?x
0.15 µm2 0.41 0.171 µm2 0.63x 0.15 µm2 0.62x 0.120 µm2  ?x 0.124 µm2  ?x 0.157 µm2  ?x

Design Rules

32 nm Microprocessors

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32 nm System on Chips

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32 nm Microarchitectures

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