Revision as of 10:01, 20 September 2017

Semiconductor lithography processes technology

1 nm 2 nm 3 nm 5 nm 7 nm 10 nm 14 nm 16 nm 20 nm 22 nm 28 nm 32 nm 40 nm 45 nm 55 nm 65 nm 80 nm 90 nm 110 nm 130 nm 150 nm 180 nm 220 nm 240 nm 250 nm 280 nm 350 nm 500 nm 600 nm 650 nm 700 nm 750 nm 800 nm 1 µm 1.2 µm 1.3 µm 1.5 µm 2 µm 2.5 µm 3 µm 3.5 µm 5 µm 6 µm 7 µm 8 µm 10 µm 16 µm 20 µm 50 µm

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The 20 nanometer (20 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 22 nm and 16 nm processes. The term "20 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 20 nm process began in 2014. This technology superseded by commercial 16 nm process.

Industry

TSMC

TSMC demonstrated their 112 Mebibit SRAM wafer from their 20 nm HKMG process at the 2013 IEEE ISSCC.

TSMC 112 Mib SRAM demo 20 nm wafer
Technology 20 nm HK-MG Metal scheme 1 Poly / 7 Metal Supply voltage 0.95 V (core) 1.8 V (i/o) Bit cell size 0.081 µm² macro configs 2048x134 MUX4 Capacity 112 Mib Test Features Row/Column Redundancy Programmable E-fuse Die Size 6400 µm x 6300 µm = 40.32 mm²

20 nm Microprocessors

• MediaTek
  • Helio
• Fujitsu
  • SPARC64
• Oracle
  • SPARC M8

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20 nm Microarchitectures

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References

• Chang, Jonathan, et al. "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-V MIN applications." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. IEEE, 2013.
• Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.