Semiconductor & Computer Engineering
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Difference between revisions of "5 nm lithography process"
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{{lithography processes}} | {{lithography processes}} | ||
| − | The '''5 nanometer (5 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 7 nm process is set to begin sometimes around | + | The '''5 nanometer (5 nm or 50 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 7 nm process is set to begin sometimes around 2020. |
The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of a transistor. | The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of a transistor. | ||
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== Industry == | == Industry == | ||
| Line 113: | Line 110: | ||
| process 4 date = | | process 4 date = | ||
| process 4 lith = EUV | | process 4 lith = EUV | ||
| − | | process 4 immersion = | + | | process 4 immersion = Yes |
| process 4 exposure = SE | | process 4 exposure = SE | ||
| process 4 wafer type = Bulk | | process 4 wafer type = Bulk | ||
| process 4 wafer size = 300 nm | | process 4 wafer size = 300 nm | ||
| − | | process 4 transistor = | + | | process 4 transistor = GAA |
| process 4 volt = | | process 4 volt = | ||
| process 4 delta from = [[7 nm]] Δ | | process 4 delta from = [[7 nm]] Δ | ||
| − | | process 4 fin pitch = | + | | process 4 fin pitch = - |
| − | | process 4 fin pitch Δ = | + | | process 4 fin pitch Δ = |
| − | | process 4 fin width = | + | | process 4 fin width = |
| − | | process 4 fin width Δ = | + | | process 4 fin width Δ = |
| − | | process 4 fin height = | + | | process 4 fin height = |
| − | | process 4 fin height Δ = | + | | process 4 fin height Δ = |
| process 4 gate len = | | process 4 gate len = | ||
| process 4 gate len Δ = | | process 4 gate len Δ = | ||
| Line 141: | Line 138: | ||
| process 4 dram Δ = | | process 4 dram Δ = | ||
}} | }} | ||
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| + | === Samsung === | ||
| + | On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a [[Gate-all-around]] (GAA) FET. This is planned for somewhere around the 5nm node but the exact timeline or specification is currently unknown. | ||
== 5 nm Microprocessors== | == 5 nm Microprocessors== | ||
Revision as of 13:57, 1 June 2017
Semiconductor lithography processes technology
The 5 nanometer (5 nm or 50 Å) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2020.
The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of a transistor.
Industry
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Intel | TSMC | GlobalFoundries | Samsung | ||||
|---|---|---|---|---|---|---|---|
| P1278? (CPU), P1279? (SoC) | |||||||
| EUV | 193 nm | EUV | EUV | ||||
| Yes | Yes | ||||||
| SE | LELELELE | SE | SE | ||||
| Bulk | Bulk | Bulk | Bulk | ||||
| 300 nm | 300 nm | 300 nm | 300 nm | ||||
| FinFET | FinFET | GAA | |||||
| Value | 10 nm Δ | Value | 10 nm Δ | Value | 10 nm Δ | Value | 7 nm Δ |
| N/A | |||||||
| ~44 nm | 0.81x | ||||||
| ~32 nm | 0.84x | ||||||
Samsung
On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere around the 5nm node but the exact timeline or specification is currently unknown.
5 nm Microprocessors
This list is incomplete; you can help by expanding it.
5 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017