Semiconductor & Computer Engineering
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Difference between revisions of "5 nm lithography process"
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| process 4 wafer size = 300 nm | | process 4 wafer size = 300 nm | ||
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== 5 nm Microprocessors== | == 5 nm Microprocessors== | ||
Revision as of 13:55, 1 June 2017
Semiconductor lithography processes technology
The 5 nanometer (5 nm) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2020s.
The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of a transistor.
Contents
Initial research
- At the 2016 IEEE International Electron Devices Meeting (IEDM), researchers from CEA-Leti presented a paper detailing the architecture for a possible 5 nm node. The researchers presented their functional vertically stacked gate-all-around (GAA) silicon NW/NS (NanoWire/NanoSheet) MOSFETs. GAA NW transistors are a highly promising candidate to succeed FinFETs as the drive current can be optimized by vertically stacking multiple horizontal nanowires.
Industry
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Intel | TSMC | GlobalFoundries | Samsung | ||||
|---|---|---|---|---|---|---|---|
| P1278? (CPU), P1279? (SoC) | |||||||
| EUV | 193 nm | EUV | EUV | ||||
| Yes | |||||||
| SE | LELELELE | SE | SE | ||||
| Bulk | Bulk | Bulk | Bulk | ||||
| 300 nm | 300 nm | 300 nm | 300 nm | ||||
| FinFET | FinFET | FinFET | |||||
| Value | 10 nm Δ | Value | 10 nm Δ | Value | 10 nm Δ | Value | 7 nm Δ |
| ~44 nm | 0.81x | ||||||
| ~32 nm | 0.84x | ||||||
5 nm Microprocessors
This list is incomplete; you can help by expanding it.
5 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017