Revision as of 13:44, 1 June 2017

Semiconductor lithography processes technology

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The 5 nanometer (5 nm) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2020s.

The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of a transistor.

Initial research

• At the 2016 IEEE International Electron Devices Meeting (IEDM), researchers from CEA-Leti presented a paper detailing the architecture for a possible 5 nm node. The researchers presented their functional vertically stacked gate-all-around (GAA) silicon NW/NS (NanoWire/NanoSheet) MOSFETs. GAA NW transistors are a highly promising candidate to succeed FinFETs as the drive current can be optimized by vertically stacking multiple horizontal nanowires.

Industry

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Samsung

On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere around the 5nm node but the exact timeline or specification is currently unknown.

5 nm Microprocessors

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5 nm Microarchitectures

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References

• TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017