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Difference between revisions of "5 nm lithography process"

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{{lithography processes}}
 
{{lithography processes}}
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The '''5 nanometer (5 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 7 nm process is set to begin sometimes around 2021 or 2022. The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to [[technology node|gate length or half pitch]].
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The '''5 nanometer (5 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 7 nm process is set to begin sometimes around 2020s.
 +
 
 +
The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of a transistor.
  
 
== Initial research ==
 
== Initial research ==
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{{future information}}
 
{{future information}}
  
 +
{{finfet nodes comp
 +
<!-- Intel -->
 +
| process 1 fab          = [[Intel]]
 +
| process 1 name        = P1278? (CPU), P1279? (SoC)
 +
| process 1 date        = &nbsp;
 +
| process 1 lith        = EUV
 +
| process 1 immersion    = &nbsp;
 +
| process 1 exposure    = SE
 +
| process 1 wafer type  = Bulk
 +
| process 1 wafer size  = 300 nm
 +
| process 1 transistor  = &nbsp;
 +
| process 1 volt        = &nbsp;
 +
| process 1 delta from  = [[10 nm]] Δ
 +
| process 1 fin pitch    = &nbsp;
 +
| process 1 fin pitch Δ  = &nbsp;
 +
| process 1 fin width    = &nbsp;
 +
| process 1 fin width Δ  = &nbsp;
 +
| process 1 fin height  = &nbsp;
 +
| process 1 fin height Δ = &nbsp;
 +
| process 1 gate len    = &nbsp;
 +
| process 1 gate len Δ  = &nbsp;
 +
| process 1 cpp          = &nbsp;
 +
| process 1 cpp Δ        = &nbsp;
 +
| process 1 mmp          = &nbsp;
 +
| process 1 mmp Δ        = &nbsp;
 +
| process 1 sram hp      = &nbsp;
 +
| process 1 sram hp Δ    = &nbsp;
 +
| process 1 sram hd      = &nbsp;
 +
| process 1 sram hd Δ    = &nbsp;
 +
| process 1 sram lv      = &nbsp;
 +
| process 1 sram lv Δ    = &nbsp;
 +
| process 1 dram        = &nbsp;
 +
| process 1 dram Δ      = &nbsp;
 +
<!-- TSMC -->
 +
| process 2 fab          = [[TSMC]]
 +
| process 2 name        = &nbsp;
 +
| process 2 date        = &nbsp;
 +
| process 2 lith        = EUV
 +
| process 2 immersion    = &nbsp;
 +
| process 2 exposure    = EUV
 +
| process 2 wafer type  = Bulk
 +
| process 2 wafer size  = 300 nm
 +
| process 2 transistor  = FinFET
 +
| process 2 volt        = &nbsp;
 +
| process 2 delta from  = [[10 nm]] Δ
 +
| process 2 fin pitch    = &nbsp;
 +
| process 2 fin pitch Δ  = &nbsp;
 +
| process 2 fin width    = &nbsp;
 +
| process 2 fin width Δ  = &nbsp;
 +
| process 2 fin height  = &nbsp;
 +
| process 2 fin height Δ = &nbsp;
 +
| process 2 gate len    = &nbsp;
 +
| process 2 gate len Δ  = &nbsp;
 +
| process 2 cpp          = ~44 nm
 +
| process 2 cpp Δ        = 0.81x
 +
| process 2 mmp          = ~32 nm
 +
| process 2 mmp Δ        = 0.84x
 +
| process 2 sram hp      = &nbsp;
 +
| process 2 sram hp Δ    = &nbsp;
 +
| process 2 sram hd      = &nbsp;
 +
| process 2 sram hd Δ    = &nbsp;
 +
| process 2 sram lv      = &nbsp;
 +
| process 2 sram lv Δ    = &nbsp;
 +
| process 2 dram        = &nbsp;
 +
| process 2 dram Δ      = &nbsp;
 +
<!-- GlobalFoundries -->
 +
| process 3 fab          = [[GlobalFoundries]]
 +
| process 3 name        = &nbsp;
 +
| process 3 date        = &nbsp;
 +
| process 3 lith        = EUV
 +
| process 3 immersion    = &nbsp;
 +
| process 3 exposure    = SE
 +
| process 3 wafer type  = Bulk
 +
| process 3 wafer size  = 300 nm
 +
| process 3 transistor  = FinFET
 +
| process 3 volt        = &nbsp;
 +
| process 3 delta from  = [[10 nm]] Δ
 +
| process 3 fin pitch    = &nbsp;
 +
| process 3 fin pitch Δ  = &nbsp;
 +
| process 3 fin width    = &nbsp;
 +
| process 3 fin width Δ  = &nbsp;
 +
| process 3 fin height  = &nbsp;
 +
| process 3 fin height Δ = &nbsp;
 +
| process 3 gate len    = &nbsp;
 +
| process 3 gate len Δ  = &nbsp;
 +
| process 3 cpp          = &nbsp;
 +
| process 3 cpp Δ        = &nbsp;
 +
| process 3 mmp          = &nbsp;
 +
| process 3 mmp Δ        = &nbsp;
 +
| process 3 sram hp      = &nbsp;
 +
| process 3 sram hp Δ    = &nbsp;
 +
| process 3 sram hd      = &nbsp;
 +
| process 3 sram hd Δ    = &nbsp;
 +
| process 3 sram lv      = &nbsp;
 +
| process 3 sram lv Δ    = &nbsp;
 +
| process 3 dram        = &nbsp;
 +
| process 3 dram Δ      = &nbsp;
 +
<!-- Samsung -->
 +
| process 4 fab          = [[Samsung]]
 +
| process 4 name        = &nbsp;
 +
| process 4 date        = &nbsp;
 +
| process 4 lith        = EUV
 +
| process 4 immersion    = Yes
 +
| process 4 exposure    = SE
 +
| process 4 wafer type  = Bulk
 +
| process 4 wafer size  = 300 nm
 +
| process 4 transistor  = GAA
 +
| process 4 volt        = &nbsp;
 +
| process 4 delta from  = [[7 nm]] Δ
 +
| process 4 fin pitch    = -
 +
| process 4 fin pitch Δ  =
 +
| process 4 fin width    =
 +
| process 4 fin width Δ  =
 +
| process 4 fin height  =
 +
| process 4 fin height Δ =
 +
| process 4 gate len    = &nbsp;
 +
| process 4 gate len Δ  = &nbsp;
 +
| process 4 cpp          = &nbsp;
 +
| process 4 cpp Δ        = &nbsp;
 +
| process 4 mmp          = &nbsp;
 +
| process 4 mmp Δ        = &nbsp;
 +
| process 4 sram hp      = &nbsp;
 +
| process 4 sram hp Δ    = &nbsp;
 +
| process 4 sram hd      = &nbsp;
 +
| process 4 sram hd Δ    = &nbsp;
 +
| process 4 sram lv      = &nbsp;
 +
| process 4 sram lv Δ    = &nbsp;
 +
| process 4 dram        = &nbsp;
 +
| process 4 dram Δ      = &nbsp;
 +
}}
  
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{{scrolling table/top|style=text-align: right; | first=Fab
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=== Samsung ===
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|Process Name
+
On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a [[Gate-all-around]] (GAA) FET. This is planned for somewhere around the 5nm node but the exact timeline or specification is currently unknown.
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|1st Production
 
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|Transistor
 
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|&nbsp;
 
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|Fin Pitch
 
−
|Fin Width
 
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|Fin Height
 
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|Contacted Gate Pitch
 
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|Interconnect Pitch (M1P)
 
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|SRAM bit cell (HP)
 
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|SRAM bit cell (HD)
 
−
}}
 
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{{scrolling table/mid}}
 
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|-
 
−
! colspan="2" | [[Intel]] !! colspan="2" | Common Platform<info>[[IBM]], [[Samsung]], [[GlobalFoundries]]</info> !! colspan="2" | [[TSMC]]
 
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|- style="text-align: center;"
 
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| colspan="2" | P1278? || colspan="2" | || colspan="2" |
 
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|- style="text-align: center;"
 
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| colspan="2" | &nbsp; || colspan="2" | || colspan="2" |
 
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|- style="text-align: center;"
 
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| colspan="6" | FinFET
 
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|-
 
−
! Value !! [[7 nm]] Δ !! Value !! [[7 nm]] Δ !! Value !! [[7 nm]] Δ
 
−
|-
 
−
| ? nm || ?x || ? nm || ?x || ? nm || ?x
 
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|-
 
−
| ? nm || ?x || ? nm || ?x || ? nm || ?x
 
−
|-
 
−
| ? nm || ?x || ? nm || ?x || ? nm || ?x
 
−
|-
 
−
| ? nm || ?x || ? nm|| ?x || ~44 nm || 0.81x
 
−
|-
 
−
| ? nm || ?x || ? nm || ?x || ~32 nm || 0.84x
 
−
|-
 
−
| ? µm² || ?x || ? µm² || ?x || ? µm² || ?x
 
−
|-
 
−
| ? µm² || ?x || ? µm² || ?x || ? µm² || ?x
 
−
{{scrolling table/end}}
 
  
 
== 5 nm Microprocessors==
 
== 5 nm Microprocessors==

Revision as of 13:43, 1 June 2017

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 5 nanometer (5 nm) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2020s.

The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of a transistor.

Initial research

  • At the 2016 IEEE International Electron Devices Meeting (IEDM), researchers from CEA-Leti presented a paper detailing the architecture for a possible 5 nm node. The researchers presented their functional vertically stacked gate-all-around (GAA) silicon NW/NS (NanoWire/NanoSheet) MOSFETs. GAA NW transistors are a highly promising candidate to succeed FinFETs as the drive current can be optimized by vertically stacking multiple horizontal nanowires.

Industry

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel TSMC GlobalFoundries Samsung
P1278? (CPU), P1279? (SoC)      
       
EUV EUV EUV EUV
      Yes
SE EUV SE SE
Bulk Bulk Bulk Bulk
300 nm 300 nm 300 nm 300 nm
  FinFET FinFET GAA
       
Value 10 nm Δ Value 10 nm Δ Value 10 nm Δ Value 7 nm Δ
            N/A
           
           
               
    ~44 nm 0.81x        
    ~32 nm 0.84x        
               
               
               
               

Samsung

On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere around the 5nm node but the exact timeline or specification is currently unknown.

5 nm Microprocessors

This list is incomplete; you can help by expanding it.

5 nm Microarchitectures

This list is incomplete; you can help by expanding it.

References

  • TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017
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