Difference between revisions of "28 nm lithography process"

Revision as of 05:02, 6 April 2017

Semiconductor lithography processes technology

1 nm • 18A
2 nm • 3 nm
5 nm • 7 nm
10 nm • 12 nm
14 nm • 16 nm
20 nm • 22 nm
28 nm • 32 nm
40 nm • 45 nm
55 nm • 65 nm
80 nm • 90 nm
110 nm • 130 nm
150 nm • 180 nm
220 nm • 240 nm
250 nm • 280 nm
350 nm • 500 nm
600 nm • 650 nm
700 nm • 750 nm
800 nm
1 µm • 1.2 µm
1.3 µm • 1.5 µm
2 µm • 2.5 µm
3 µm • 3.5 µm
5 µm • 6 µm
7 µm • 8 µm
10 µm • 16 µm
20 µm • 50 µm

The 28 nanometer (28 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.

Industry


Process Name
1st Production
Litho- graphy	Lithography
	Immersion
	Exposure
Wafer	Type
Wafer	Size
Tran- sistor	Type
Tran- sistor	Voltage
Metal Layers

Gate Length (L_g)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell	High-Perf (HP)
	High-Density (HD)
	Low-Voltage (LV)
DRAM bitcell	eDRAM

 TSMC
 Common Platform Alliance The Common Platform Alliance is a joint collaboration between IBM, Samsung, GlobalFoundries, Toshiba, NEC, STMicroelectronics, Infineon Technologies, Chartered Semiconductor Manufacturing, Renasas

 UMC

 28LP, 28HPL, 28HP
 28LP, 28LPP, 28SLP
 28HPC, 28HLP, 28HPC+, 28µLP

 2013
 2014
 2014

 193 nm
 193 nm
 193 nm

 Yes
 Yes
 Yes

 DP
 DP
 DP

 Bulk
 Bulk
 Bulk

 300 mm
 300 mm
 300 mm

 Planar
 Planar
 Planar

 1 V, 0.8 V
 1 V, 0.85 V
 0.9 V, 1.05 V, 0.7 V

 10
 10
 10

 Value 
 32 nm Δ
 Value 
 32 nm Δ
 Value 
 40 nm Δ

 24 nm 
  
 28 nm 
  
 33 nm 
  
 117 nm 
  
 113.4 nm 
  
 120 nm 
  
 90 nm 
  
 90 nm 
  
 90 nm 
  
 0.152 µm² 
  
 0.127 µm² 
  
 0.120 µm² 
  
 0.124 µm² 
  
 0.155 µm² 
  
 0.197 µm²

28 nm Microprocessors

AMD
- A8
- A10
Intel (Fab'ed by TSMC)
- Atom x3
MediaTek
- Helio
Phytium
- FT-1500A
PEZY
- PEZY-SC
- PEZY-SCnp
Xiaomi
- Surge

This list is incomplete; you can help by expanding it.

28 nm Microarchitectures

AMD
- Steamroller
- Excavator
ARM Holdings
- Cortex-A53
Phytium
- Xiaomi

This list is incomplete; you can help by expanding it.

References

Samsung foundry solution for 32 & 28 nm
Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009.
Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
Arnaud, F., et al. "Competitive and cost effective high-k based 28nm CMOS technology for low power applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
Yuan, J., et al. "Performance elements for 28nm gate length bulk devices with gate first high-k metal gate." Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on. IEEE, 2010.
Liang, C. W., et al. "A 28nm poly/SiON CMOS technology for low-power SoC applications." VLSI Technology (VLSIT), 2011 Symposium on. IEEE, 2011.
James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.

@@ Line 6: / Line 6: @@
 <!-- TSMC -->
   | process 1 fab          = [[TSMC]]
-  | process 1 name         = &nbsp;
+  | process 1 name         = 28LP, 28HPL, 28HP
-  | process 1 date         = &nbsp;
+  | process 1 date         = 2013
-  | process 1 lith         = &nbsp;
+  | process 1 lith         = 193 nm
-  | process 1 immersion    = &nbsp;
+  | process 1 immersion    = Yes
-  | process 1 exposure     = &nbsp;
+  | process 1 exposure     = DP
   | process 1 wafer type   = Bulk
   | process 1 wafer size   = 300 mm
   | process 1 transistor   = Planar
-  | process 1 volt         = &nbsp;
+  | process 1 volt         = 1 V, 0.8 V
   | process 1 layers       = 10
   | process 1 delta from   = [[32 nm]] Δ
-  | process 1 gate len     = &nbsp;
+  | process 1 gate len     = 24 nm
   | process 1 gate len Δ   = &nbsp;
-  | process 1 cpp          = &nbsp;
+  | process 1 cpp          = 117 nm
   | process 1 cpp Δ        = &nbsp;
-  | process 1 mmp          = &nbsp;
+  | process 1 mmp          = 90 nm
   | process 1 mmp Δ        = &nbsp;
   | process 1 sram hp      = &nbsp;
   | process 1 sram hp Δ    = &nbsp;
-  | process 1 sram hd      = &nbsp;
+  | process 1 sram hd      = 0.127 µm²
   | process 1 sram hd Δ    = &nbsp;
-  | process 1 sram lv      = &nbsp;
+  | process 1 sram lv      = 0.155 µm²
   | process 1 sram lv Δ    = &nbsp;
   | process 1 dram         = &nbsp;
   | process 1 dram Δ       = &nbsp;
 <!-- IBM -->
-  | process 2 fab          = [[Common Platform Alliance ]]<info>The '''Common Platform Alliance '' is a joint collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[Toshiba]], [[NEC]], [[STMicroelectronics]], [[Infineon Technologies]], [[Chartered Semiconductor Manufacturing]]</info>
+  | process 2 fab          = [[Common Platform Alliance ]]<info>The '''Common Platform Alliance''' is a joint collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[Toshiba]], [[NEC]], [[STMicroelectronics]], [[Infineon Technologies]], [[Chartered Semiconductor Manufacturing]], [[Renasas]]</info>
-  | process 2 name         = 28LP/28LPP/28SLP
+  | process 2 name         = 28LP, 28LPP, 28SLP
-  | process 2 date         = 2
+  | process 2 date         = 2014
-  | process 2 lith         = &nbsp;
+  | process 2 lith         = 193 nm
-  | process 2 immersion    = &nbsp;
+  | process 2 immersion    = Yes
-  | process 2 exposure     = &nbsp;
+  | process 2 exposure     = DP
   | process 2 wafer type   = Bulk
   | process 2 wafer size   = 300 mm
   | process 2 transistor   = Planar
-  | process 2 volt         = 1 V
+  | process 2 volt         = 1 V, 0.85 V
-  | process 2 layers       = &nbsp;
+  | process 2 layers       = 10
   | process 2 delta from   = [[32 nm]] Δ
-  | process 2 gate len     = &nbsp;
+  | process 2 gate len     = 28 nm
   | process 2 gate len Δ   = &nbsp;
   | process 2 cpp          = 113.4 nm
@@ Line 58: / Line 58: @@
   | process 2 dram         = &nbsp;
   | process 2 dram Δ       = &nbsp;
+<!-- UMC -->
+ | process 3 fab          = [[UMC]]
+ | process 3 name         = 28HPC, 28HLP, 28HPC+, 28µLP
+ | process 3 date         = 2014
+ | process 3 lith         = 193 nm
+ | process 3 immersion    = Yes
+ | process 3 exposure     = DP
+ | process 3 wafer type   = Bulk
+ | process 3 wafer size   = 300 mm
+ | process 3 transistor   = Planar
+ | process 3 volt         = 0.9 V, 1.05 V, 0.7 V
+ | process 3 layers       = 10
+ | process 3 delta from   = [[40 nm]] Δ
+ | process 3 gate len     = 33 nm
+ | process 3 gate len Δ   = &nbsp;
+ | process 3 cpp          = 120 nm
+ | process 3 cpp Δ        = &nbsp;
+ | process 3 mmp          = 90 nm
+ | process 3 mmp Δ        = &nbsp;
+ | process 3 sram hp      = &nbsp;
+ | process 3 sram hp Δ    = &nbsp;
+ | process 3 sram hd      = 0.124 µm²
+ | process 3 sram hd Δ    = &nbsp;
+ | process 3 sram lv      = &nbsp;
+ | process 3 sram lv Δ    = &nbsp;
+ | process 3 dram         = &nbsp;
+ | process 3 dram Δ       = &nbsp;
 }}
@@ Line 90: / Line 117: @@
 == References ==
+* [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]]
 * Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009.
 * Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
+* Arnaud, F., et al. "Competitive and cost effective high-k based 28nm CMOS technology for low power applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
+* Yuan, J., et al. "Performance elements for 28nm gate length bulk devices with gate first high-k metal gate." Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on. IEEE, 2010.
+* Liang, C. W., et al. "A 28nm poly/SiON CMOS technology for low-power SoC applications." VLSI Technology (VLSIT), 2011 Symposium on. IEEE, 2011.
 * James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.
-* [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]]

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