Semiconductor & Computer Engineering
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== Industry == | == Industry == | ||
| − | In ISSCC 2017, the memory group at [[TSMC]] detailed their test 128 MiB SRAM chip which featured a 42. | + | In ISSCC 2017, the memory group at [[TSMC]] detailed their test 128 MiB SRAM chip which featured a 42.64 mm² die<ref name="tsmc" />. The chip is manufactured on TSMC's 7nm HK-MG FinFET process. The chip, which initially debuted in last year's ISSCC, makes use of 0.027 µm² bit cells, currently the smallest such cells in risk production. The over die is 0.34x smaller than their [[16 nm process]] version. At the same conference, [[Samsung]] detailed limited use for [[EUV]] in their 7nm node, though not much more is known. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. |
{{future information}} | {{future information}} | ||
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{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
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| ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x | | ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x | ||
|- | |- | ||
| − | | ? µm² || ?x || ? µm² || ?x || 0.027 µm²<ref> | + | | ? µm² || ?x || ? µm² || ?x || 0.027 µm²<ref name="tsmc">Chang, Jonathan, et al. "12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V MIN applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.</ref> || ?x || ? µm² || ?x || ? µm² || ?x |
{{scrolling table/end}} | {{scrolling table/end}} | ||
| + | |||
| + | === TSMC === | ||
| + | TSMC demonstrated their 256 Mebibit [[SRAM]] wafer from their 7nm HKMG FinFET process. Their chip makes use of 34% of the area of their [[16 nm process]] demo chip counterpart. | ||
| + | {| class="collapsible collapsed wikitable" | ||
| + | |- | ||
| + | ! colspan="2" | TSMC 256Mb SRAM wafer<ref name="tsmc" /> | ||
| + | |- | ||
| + | | | ||
| + | <table class="wikitable"> | ||
| + | <tr><th>Technology</th><td>7 nm HK-MG FinFET</td></tr> | ||
| + | <tr><th>Metal scheme</th><td>1P7M</td></tr> | ||
| + | <tr><th>Supply voltage</th><td>0.75 V (core)<br>1.8 V (i/o)</td></tr> | ||
| + | <tr><th>Bit cell size</th><td>0.027 µm²</td></tr> | ||
| + | <tr><th>macro configs</th><td>4096x32 MUX16<br>258 bits/BL<br>272 bits/WL</td></tr> | ||
| + | <tr><th>Capacity</th><td>256 Mib</td></tr> | ||
| + | <tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr> | ||
| + | <tr><th>Die Size</th><td>5903 µm x 7223 µm = 42.64 mm^2</td></tr> | ||
| + | </table> | ||
| + | | [[File:tsmc 7nm SRAM block.png]] | ||
| + | |} | ||
== 7 nm Microprocessors== | == 7 nm Microprocessors== | ||
Revision as of 16:58, 10 March 2017
Semiconductor lithography processes technology
The 7 nanometer (7 nm) lithography process is a full node semiconductor manufacturing process following the 10 nm process node. The term "7 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial mass production of integrated circuit using 7 nm process is set to begin sometimes in 2019 or 2020. This technology will be replaced by 5 nm process around 2022.
Industry
In ISSCC 2017, the memory group at TSMC detailed their test 128 MiB SRAM chip which featured a 42.64 mm² die[1]. The chip is manufactured on TSMC's 7nm HK-MG FinFET process. The chip, which initially debuted in last year's ISSCC, makes use of 0.027 µm² bit cells, currently the smallest such cells in risk production. The over die is 0.34x smaller than their 16 nm process version. At the same conference, Samsung detailed limited use for EUV in their 7nm node, though not much more is known. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process.
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Fab |
|---|
| Process Name |
| 1st Production |
| |
| Fin Pitch |
| Fin Width |
| Fin Height |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell (HP) |
| SRAM bit cell (HD) |
| Intel | Samsung | TSMC | GlobalFoundries | IBM | |||||
|---|---|---|---|---|---|---|---|---|---|
| P1276 | |||||||||
| Value | 10 nm Δ | Value | 10 nm Δ | Value | 10 nm Δ | Value | 10 nm Δ | Value | 10 nm Δ |
| ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | 48 nm[2] | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | 36 nm[3] | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x |
| ? µm² | ?x | ? µm² | ?x | 0.027 µm²[1] | ?x | ? µm² | ?x | ? µm² | ?x |
TSMC
TSMC demonstrated their 256 Mebibit SRAM wafer from their 7nm HKMG FinFET process. Their chip makes use of 34% of the area of their 16 nm process demo chip counterpart.
| TSMC 256Mb SRAM wafer[1] | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| ||||||||||||||||
7 nm Microprocessors
This list is incomplete; you can help by expanding it.
7 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- ↑ 1.0 1.1 1.2 Chang, Jonathan, et al. "12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V MIN applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.
- ↑ Samsung, IEEE International Electron Devices Meeting (IEDM) 2016
- ↑ Samsung, IEEE International Electron Devices Meeting (IEDM) 2016