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Difference between revisions of "65 nm lithography process"

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| Interconnect Pitch (M1P) || 210 nm || 0.95x
 
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| [[SRAM]] bit cell || 0.570 µm<sup>2</sup> || 0.61x
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| [[SRAM]] bit cell || 0.570 µm<sup>2</sup> || 0.57x
 
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Revision as of 19:07, 23 April 2016

The 65 nm lithography process is a full node semiconductor manufacturing process following the 80 nm process stopgap. Commercial integrated circuit manufacturing using 65 nm process began in 2006. This technology was superseded by the 55 nm process (HN) / 45 nm process (FN) in 2007.

Industry

Intel

Measurement Scaling from 90 nm
Contacted Gate Pitch 220 nm 0.85x
Interconnect Pitch (M1P) 210 nm 0.95x
SRAM bit cell 0.570 µm2 0.57x
Design Rules
Layer Pitch Thick Aspect Ratio
Isolation 220 nm 320 nm -
Polysilicon 220 nm 90 nm -
Contacted Gate 220 nm -
Metal 1 210 nm 170 nm 1.6
Metal 2 210 nm 190 nm 1.8
Metal 3 220 nm 200 nm 1.8
Metal 4 280 nm 250 nm 1.8
Metal 5 330 nm 300 nm 1.8
Metal 6 480 nm 430 nm 1.8
Metal 7 720 nm 650 nm 1.8
Metal 8 1.80 µm 975 nm 1.8

65 nm Microprocessors

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65 nm System on Chips

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65 nm Microarchitectures

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