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Difference between revisions of "16 nm lithography process"

(TSMC)
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<table class="wikitable">
 
<table class="wikitable">
 
<tr><th>Technology</th><td>16 nm HK-MG FinFET</td></tr>
 
<tr><th>Technology</th><td>16 nm HK-MG FinFET</td></tr>
<tr><th>Metal scheme</th><td>1P7M</td></tr>
+
<tr><th>Metal scheme</th><td>1 Poly  / 7 Metal</td></tr>
 
<tr><th>Supply voltage</th><td>0.85 V (core)<br>1.8 V (i/o)</td></tr>
 
<tr><th>Supply voltage</th><td>0.85 V (core)<br>1.8 V (i/o)</td></tr>
 
<tr><th>Bit cell size</th><td>0.07 µm²</td></tr>
 
<tr><th>Bit cell size</th><td>0.07 µm²</td></tr>

Revision as of 17:22, 10 March 2017

The 16 nanometer (16 nm) lithography process is a full node semiconductor manufacturing process following the 20 nm process stopgap. Commercial integrated circuit manufacturing using 16 nm process began in 2014. The term "16 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with 10 nm process in 2017.

Industry

Fab
Wafer​
 ​
Fin Pitch​
Fin Width​
Fin Height​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
TSMC
300mm
Value[1] 20 nm Δ
48 nm N/A
 ? nm
37 nm
90 nm 1.03x
70 nm 1.09x
0.07 µm²[2] 0.55x

TSMC

TSMC demonstrated their 128 Mebibit SRAM wafer from their 16 nm HKMG FinFET process at the 2014 IEEE ISSCC.

16 nm Microprocessors

This list is incomplete; you can help by expanding it.

16 nm Microarchitectures

This list is incomplete; you can help by expanding it.

References

  1. TechInsights/Chipworks, Kevin Gibb, The ConFab 2016
  2. 2.0 2.1 Chen, Yen-Huei, et al. "A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 170-177.