From WikiChip
Difference between revisions of "16 nm lithography process"
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<tr><th>Technology</th><td>16 nm HK-MG FinFET</td></tr> | <tr><th>Technology</th><td>16 nm HK-MG FinFET</td></tr> | ||
− | <tr><th>Metal scheme</th><td> | + | <tr><th>Metal scheme</th><td>1 Poly / 7 Metal</td></tr> |
<tr><th>Supply voltage</th><td>0.85 V (core)<br>1.8 V (i/o)</td></tr> | <tr><th>Supply voltage</th><td>0.85 V (core)<br>1.8 V (i/o)</td></tr> | ||
<tr><th>Bit cell size</th><td>0.07 µm²</td></tr> | <tr><th>Bit cell size</th><td>0.07 µm²</td></tr> |
Revision as of 17:22, 10 March 2017
The 16 nanometer (16 nm) lithography process is a full node semiconductor manufacturing process following the 20 nm process stopgap. Commercial integrated circuit manufacturing using 16 nm process began in 2014. The term "16 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with 10 nm process in 2017.
Industry
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Wafer |
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Fin Pitch |
Fin Width |
Fin Height |
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell |
TSMC
TSMC demonstrated their 128 Mebibit SRAM wafer from their 16 nm HKMG FinFET process at the 2014 IEEE ISSCC.
TSMC 128 Mib SRAM demo wafer[2] | |||||||||||||||||
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16 nm Microprocessors
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16 nm Microarchitectures
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