Semiconductor & Computer Engineering
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Difference between revisions of "10 nm lithography process"
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== Industry == | == Industry == | ||
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
| + | |Process Name | ||
| + | |1st Production | ||
| | | | ||
|Fin Pitch | |Fin Pitch | ||
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! colspan="2" | [[Intel]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] | ! colspan="2" | [[Intel]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] | ||
| + | |- style="text-align: center;" | ||
| + | | colspan="2" | P1274 || colspan="2" | || colspan="2" | | ||
| + | |- style="text-align: center;" | ||
| + | | colspan="2" | || colspan="2" | || colspan="2" | | ||
|- | |- | ||
! Value !! [[14 nm]] Δ !! Value !! [[14 nm]] Δ !! Value !! [[16 nm]] Δ | ! Value !! [[14 nm]] Δ !! Value !! [[14 nm]] Δ !! Value !! [[16 nm]] Δ | ||
Revision as of 18:17, 24 April 2016
Semiconductor lithography processes technology
The 10 nm lithography process is a full node semiconductor manufacturing process following the 14 nm process stopgap. Commercial integrated circuit manufacturing using 10 nm process is set to begin in 2017. This technology is set to be replaced by 7 nm process 2019.
Industry
| Fab |
|---|
| Process Name |
| 1st Production |
| |
| Fin Pitch |
| Fin Width |
| Fin Height |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell (HP) |
| SRAM bit cell (HD) |
| Intel | Samsung | TSMC | |||
|---|---|---|---|---|---|
| P1274 | |||||
| Value | 14 nm Δ | Value | 14 nm Δ | Value | 16 nm Δ |
| ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | ? nm | ?x | ? nm | ?x |
| 55 nm | 0.78x | 64 nm | 0.82x | 70 nm | 0.78x |
| 38 nm | 0.74x | 48 nm | 0.75x | 46 nm | 0.72x |
| ? µm2 | ?x | 0.049 µm2 | 0.61x | ? µm2 | ?x |
| ? µm2 | ?x | 0.040 µm2 | 0.63x | ? µm2 | ?x |
10 nm Microprocessors
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10 nm System on Chips
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10 nm Microarchitectures
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