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Difference between revisions of "20 nm lithography process"

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| Contacted Gate Pitch || 64 nm || 0.71x
 
| Contacted Gate Pitch || 64 nm || 0.71x
 
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| Interconnect Pitch (M1P) || 64 nm || 0.67
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| Interconnect Pitch (M1P) || 64 nm || 0.67x
 
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| [[SRAM]] bit cell || ? µm<sup>2</sup> || ?x
 
| [[SRAM]] bit cell || ? µm<sup>2</sup> || ?x

Revision as of 21:47, 23 April 2016

basic wafer drawing.svg Semiconductor lithography processes technology
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The 20 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 22 nm and 16 nm processes. Commercial integrated circuit manufacturing using 20 nm process began in 2014. This technology superseded by commercial 16 nm process.

Industry

Samsung

Measurement Scaling from 28 nm
Contacted Gate Pitch 64 nm 0.71x
Interconnect Pitch (M1P) 64 nm 0.67x
SRAM bit cell  ? µm2  ?x

20 nm Microprocessors

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20 nm System on Chips

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20 nm Microarchitectures

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