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Difference between revisions of "1.5 µm lithography process"
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Latest revision as of 23:04, 20 May 2018
The 1.5 µm lithography process was the semiconductor process technology used by the major semiconductor companies in the mid 1980s. This process had an effective channel length of roughly 1.5 µm between the source and drain. By the late 80s this process was replaced by 1.3 µm, 1.2 µm, and 1 µm processes.
Industry[edit]
Fab |
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Process Name |
1st Production |
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
Metal Layers |
SRAM bit cell |
Wafer |
Intel | Intel | Intel | HP | AMD | DEC |
---|---|---|---|---|---|
HMOS-II | HMOS-E | P646 (CHMOS III) | NMOS III | CMOS-2 | |
1982 | 1982 | 1985 | 1981 | 1982 | |
? nm | ? nm | ? nm | 1.5 µm | ||
? nm | ? nm | ? nm | 2.5 µm | ||
2 | ? | 2 | 2 | 2 | 2 |
? µm² | ? µm² | ? µm² | ? µm² | ? µm² | |
125 mm | 150 mm |
HP[edit]
[show] HP NMOS-III Design Rules |
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DEC[edit]
DEC operated their 1.5 µm process (CMOS-2) at their Hudson foundry. This 2 ML process had an effective channel length of 0.9 µm with a polycide width of 1.5 µm (1.5 µm spacing) and a TOX of 22.5 nm.
[show] DEC Design Rules |
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1.5 µm Microprocessors[edit]
This list is incomplete; you can help by expanding it.
1.5 µm Microarchitectures[edit]
This list is incomplete; you can help by expanding it.
- DEC