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Difference between revisions of "90 nm lithography process"
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== Industry == | == Industry == | ||
+ | Introduced in late 2002, Intel's 90 nm process became the first volume production to introduce [[strained silicon]] transistors. | ||
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
|Process Name | |Process Name | ||
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| 220 nm || 0.63x || 240 nm || 0.71x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x | | 220 nm || 0.63x || 240 nm || 0.71x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x | ||
|- | |- | ||
− | | 1.0 | + | | 1.0 µm² || 0.50x || 0.999 µm² || 0.47x || 0.999 µm² || ?x || 1.07 µm² || 0.54x || 0.999 µm² || ?x || ? µm² || ?x || ? µm² || ?x |
|- | |- | ||
− | | || || || || || || || || 0.19 | + | | || || || || 0.275 µm² || || || || 0.19 µm² || ?x || || || || |
{{scrolling table/end}} | {{scrolling table/end}} | ||
Line 50: | Line 51: | ||
* Cavium | * Cavium | ||
** {{cavium|OCTEON Plus}} | ** {{cavium|OCTEON Plus}} | ||
+ | * HAL (Fujitsu) | ||
+ | ** {{hal|SPARC64 V}} | ||
* IBM | * IBM | ||
** {{ibm|PowerPC 970}} | ** {{ibm|PowerPC 970}} | ||
+ | * Loongson | ||
+ | ** {{loongson|Godson 2}} | ||
+ | * Qualcomm | ||
+ | ** {{qualcomm|MSM6xxx}} | ||
* Sun | * Sun | ||
** {{sun|UltraSPARC T1}} | ** {{sun|UltraSPARC T1}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
* Intel | * Intel | ||
** {{intel|Pentium 4 Extreme Edition}} | ** {{intel|Pentium 4 Extreme Edition}} | ||
** {{intel|Pentium M}} | ** {{intel|Pentium M}} | ||
** {{intel|Pentium D}} | ** {{intel|Pentium D}} | ||
+ | ** {{intel|EP80579}} | ||
+ | * STMicroelectronics | ||
+ | ** STM32 F4 | ||
+ | ** STM32 F7 | ||
+ | ** STM32 G0 | ||
+ | ** STM32 G4 | ||
{{expand list}} | {{expand list}} | ||
Line 70: | Line 78: | ||
* ARM | * ARM | ||
** {{armh|ARM7|l=arch}} | ** {{armh|ARM7|l=arch}} | ||
+ | * IBM | ||
+ | ** {{ibm|z9|l=arch}} | ||
+ | * Intel | ||
+ | ** {{intel|Pentium M|l=arch}} | ||
+ | * VIA Technologies | ||
+ | ** {{via|Esther|l=arch}} | ||
{{expand list}} | {{expand list}} | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:samsung foundry - 45, 65, 90 (August, 2007).pdf|Samsung foundry - 45 nm, 65 nm, 90 nm guide (August, 2007)]] | ||
+ | |||
+ | [[category:lithography]] |
Latest revision as of 02:09, 17 August 2023
The 90 nanometer (90 nm) lithography process is a full node semiconductor manufacturing process following the 110 nm process stopgap. Commercial integrated circuit manufacturing using 90 nm process began in 2003. This technology was superseded by the 80 nm process (HN) / 65 nm process (FN) in 2006.
Industry[edit]
Introduced in late 2002, Intel's 90 nm process became the first volume production to introduce strained silicon transistors.
Fab |
---|
Process Name |
1st Production |
Type |
Wafer |
Metal Layers |
|
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell |
DRAM bit cell |
Intel | TSMC | Samsung | Fujitsu | IBM / Toshiba / Sony / AMD / Chartered | Motorola | TI | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
P1262 | CS-100 / CS-101 | HiPerMOS 8 | |||||||||||
2002 | 2003 | 2003 | 2004 | 2003 | 2004 | 2005 | |||||||
Bulk | PDSOI | Bulk | |||||||||||
300mm | |||||||||||||
7 | 10 | 9 | |||||||||||
Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ |
260 nm | 0.82x | 240 nm | 0.77x | 245 nm | 0.70x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
220 nm | 0.63x | 240 nm | 0.71x | 245 nm | 0.70x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
1.0 µm² | 0.50x | 0.999 µm² | 0.47x | 0.999 µm² | ?x | 1.07 µm² | 0.54x | 0.999 µm² | ?x | ? µm² | ?x | ? µm² | ?x |
0.275 µm² | 0.19 µm² | ?x |
90 nm Microprocessors[edit]
- AMD
- Cavium
- HAL (Fujitsu)
- IBM
- Loongson
- Qualcomm
- Sun
- Intel
- STMicroelectronics
- STM32 F4
- STM32 F7
- STM32 G0
- STM32 G4
This list is incomplete; you can help by expanding it.
90 nm Microarchitectures[edit]
This list is incomplete; you can help by expanding it.