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From WikiChip
Esther - Microarchitectures - VIA Technologies
| Edit Values | |
| Esther µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | VIA Technologies |
| Manufacturer | TSMC |
| Process | 90 nm |
| Core Configs | 1 |
| Pipeline | |
| Stages | 16 |
| Instructions | |
| ISA | x86-32 |
| Succession | |
Esther is the successor to Nehemiah, an x86 microarchitecture designed by VIA Technologies for low power devices.
Retrieved from "https://en.wikichip.org/w/index.php?title=via_technologies/microarchitectures/esther&oldid=72525"
Facts about "Esther - Microarchitectures - VIA Technologies"
| codename | Esther + |
| core count | 1 + |
| designer | VIA Technologies + |
| full page name | via technologies/microarchitectures/esther + |
| instance of | microarchitecture + |
| instruction set architecture | x86-32 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Esther + |
| pipeline stages | 16 + |
| process | 90 nm (0.09 μm, 9.0e-5 mm) + |