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Difference between revisions of "500 nm lithography process"
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| ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x | | ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x | ||
|- | |- | ||
− | | 44 | + | | 44 µm² || 0.40x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x |
{{scrolling table/end}} | {{scrolling table/end}} | ||
+ | |||
+ | === DEC === | ||
+ | {{see also|dec/process|l1=DEC's Process Technology History}} | ||
+ | DEC's half-micron process, '''CMOS-5''', which was used for their microprocessors such as the {{decc|Alpha 21164|l=arch}} used a Cabalt di-silicide in diffusion and poly with a channel length of 0.365 µm with a T<sub>OX</sub> of 9 nm along with 4 metal layers of AlCu (Aluminum Copper). The process had a Vtn/p = 0.5/-0.5 V and a supply voltage of 3.3 V. | ||
+ | |||
+ | {| class="wikitable collapsible collapsed" | ||
+ | |- | ||
+ | ! colspan="3" | DEC's Design Rules | ||
+ | |- | ||
+ | ! Layer !! Pitch !! Thickness | ||
+ | |- | ||
+ | | M1 || 1.50 µm || 0.84 µm | ||
+ | |- | ||
+ | | M2 || 1.75 µm || 0.84 µm | ||
+ | |- | ||
+ | | M3 || 5.00 µm || 1.53 µm | ||
+ | |- | ||
+ | | M4 || 6.00 µm || 1.53 µm | ||
+ | |} | ||
== 500 nm Microprocessors == | == 500 nm Microprocessors == | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
* AMD | * AMD | ||
** {{amd|Am486}} | ** {{amd|Am486}} | ||
− | ** {{amd|K5}} | + | ** {{amd|K5}} ("SSA/5" models only) |
+ | * Cyrix | ||
+ | ** {{cyrix|6x86}} | ||
* DEC | * DEC | ||
** {{decc|Alpha 21164}} | ** {{decc|Alpha 21164}} | ||
** {{decc|Alpha 21064A}} | ** {{decc|Alpha 21064A}} | ||
** {{decc|Alpha 21164PC}} | ** {{decc|Alpha 21164PC}} | ||
+ | * Exponential | ||
+ | ** {{expotech|X704}} | ||
* Fujitsu | * Fujitsu | ||
** {{fujitsu|microSPARC II}} ("Swift") | ** {{fujitsu|microSPARC II}} ("Swift") | ||
− | |||
− | |||
* Hitachi | * Hitachi | ||
** {{hitachi|harp-1}} | ** {{hitachi|harp-1}} | ||
+ | * HP | ||
+ | ** {{hp|PA-7200}} ("Thunderbird") | ||
+ | ** {{hp|PA-7300LC}} | ||
+ | ** {{hp|PA-8000}} ("Onyx", "Vulcan") | ||
* IBM | * IBM | ||
** {{ibm|PowerPC 601v}} | ** {{ibm|PowerPC 601v}} | ||
Line 57: | Line 75: | ||
** {{ibm|PowerPC 603}} | ** {{ibm|PowerPC 603}} | ||
** {{ibm|PowerPC 603e}} | ** {{ibm|PowerPC 603e}} | ||
+ | * Intel | ||
+ | ** {{intel|Pentium Pro}} | ||
* NexGen | * NexGen | ||
** {{nexgen|Nx586}} | ** {{nexgen|Nx586}} | ||
− | * | + | * Qualcomm |
− | ** {{ | + | ** {{qualcomm|MSM2}} |
+ | * Ross | ||
+ | ** {{ross|hyperSPARC}} ("Colorado 2") | ||
+ | * Sun | ||
+ | ** {{sun|microSPARC II}}, 1994 | ||
+ | ** {{sun|UltraSPARC}} | ||
{{expand list}} | {{expand list}} | ||
== 500 nm Microarchitectures == | == 500 nm Microarchitectures == | ||
+ | * AMD | ||
+ | ** {{amd|K5|l=arch}} | ||
+ | * DEC | ||
+ | ** {{decc|Alpha 21164|l=arch}} | ||
+ | * Intel | ||
+ | ** {{intel|80186|l=arch}} (embedded [[IP cores]] only) | ||
{{expand list}} | {{expand list}} | ||
+ | |||
+ | [[category:lithography]] |
Latest revision as of 05:15, 20 July 2018
The 500 nanometer (500 nm) lithography process is a full node semiconductor manufacturing process following the 600 nm process. Commercial integrated circuit manufacturing using 500 nm process began in 1992. 500 nm and was phased out and later replaced by 350 nm in 1995.
Industry[edit]
Fab |
---|
Process Name |
1st Production |
Metal Layers |
|
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell |
Intel | AMD | DEC | Fujitsu | Hitachi | HP | IBM | TI | Motorola | National (BiCMOS) | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
P852 | CS-24 | CMOS-5 | CMOS14C | CMOS-5X | HiPerMOS 1 | ABiC V | |||||||||||||
1994 | 1993 | 1993 | 1994 | 1994 | 1996 | 1994 | 1995 | 1995 | |||||||||||
3 | 4 | 3 | 4 | 5 | 4 | 4 | |||||||||||||
Value | 800 nm Δ | Value | 800 nm Δ | Value | 800 nm Δ | Value | 800 nm Δ | Value | 800 nm Δ | Value | 800 nm Δ | Value | 800 nm Δ | Value | 800 nm Δ | Value | 800 nm Δ | Value | 800 nm Δ |
? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
44 µm² | 0.40x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x |
DEC[edit]
- See also: DEC's Process Technology History
DEC's half-micron process, CMOS-5, which was used for their microprocessors such as the Alpha 21164 used a Cabalt di-silicide in diffusion and poly with a channel length of 0.365 µm with a TOX of 9 nm along with 4 metal layers of AlCu (Aluminum Copper). The process had a Vtn/p = 0.5/-0.5 V and a supply voltage of 3.3 V.
DEC's Design Rules | ||
---|---|---|
Layer | Pitch | Thickness |
M1 | 1.50 µm | 0.84 µm |
M2 | 1.75 µm | 0.84 µm |
M3 | 5.00 µm | 1.53 µm |
M4 | 6.00 µm | 1.53 µm |
500 nm Microprocessors[edit]
- AMD
- Cyrix
- DEC
- Exponential
- Fujitsu
- microSPARC II ("Swift")
- Hitachi
- HP
- IBM
- Intel
- NexGen
- Qualcomm
- Ross
- hyperSPARC ("Colorado 2")
- Sun
- microSPARC II, 1994
- UltraSPARC
This list is incomplete; you can help by expanding it.
500 nm Microarchitectures[edit]
- AMD
- DEC
- Intel
This list is incomplete; you can help by expanding it.