Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "10 µm lithography process"
m (Bot: Automated text replacement (-Category:Lithography +category:lithography)) |
|||
| (16 intermediate revisions by 3 users not shown) | |||
| Line 1: | Line 1: | ||
{{lithography processes}} | {{lithography processes}} | ||
| − | The '''10 µm lithography process''' was the [[semiconductor process]] technology used by the major semiconductor companies during the years of 1967 and 1973. The typical [[wafer]] | + | The '''10 µm lithography process''' was the [[semiconductor process]] technology used by the major semiconductor companies during the years of 1967 and 1973. This process had an effective channel length of roughly 10 µm between the source and drain (Poly-SI channel implant). The typical [[wafer size]] for this process at companies such as [[Fairchild]] and [[TI]] was 2-inch (51 mm). |
| + | |||
| + | == Industry == | ||
| + | {{scrolling table/top|style=text-align: right; | first=Fab | ||
| + | |Process Name | ||
| + | |1st Production | ||
| + | |Contacted Gate Pitch | ||
| + | |Interconnect Pitch | ||
| + | |Metal Layers | ||
| + | |Technology | ||
| + | |Wafer | ||
| + | }} | ||
| + | {{scrolling table/mid}} | ||
| + | |- | ||
| + | ! [[Intel]] !! [[TI]] !! [[RCA]] !! [[Fairchild]] !! [[National Semiconductor|National]]!! [[microsystems international|MIL]] | ||
| + | |- style="text-align: center;" | ||
| + | | || || || || || | ||
| + | |- style="text-align: center;" | ||
| + | | 1970 || 1969 || 1969 || || || 1969 | ||
| + | |- | ||
| + | | ? nm || ? nm || ? nm || ? nm || ? nm || ? nm | ||
| + | |- | ||
| + | | ? nm || ? nm || ? nm || ? nm || ? nm || ? nm | ||
| + | |- | ||
| + | | 2 || 2 || 2 || 2 || || | ||
| + | |- | ||
| + | | PMOS || PMOS || CMOS || PMOS || PMOS || | ||
| + | |- | ||
| + | | 51 mm || || || || || | ||
| + | {{scrolling table/end}} | ||
== 10 µm Microprocessors == | == 10 µm Microprocessors == | ||
| Line 6: | Line 35: | ||
** {{intel|MCS-4|4004}} | ** {{intel|MCS-4|4004}} | ||
** {{intel|MCS-40|4040}} | ** {{intel|MCS-40|4040}} | ||
| + | ** {{intel|MCS-8|8008}} | ||
| + | * National | ||
| + | ** {{national|IMP-4}} | ||
| + | {{expand list}} | ||
| + | |||
| + | |||
| + | {{#ask: | ||
| + | [[instance of::microprocessor]] | ||
| + | [[process::10 µm]] | ||
| + | | ?name | ||
| + | | ?process | ||
| + | | ?manufacturer | ||
| + | | format=broadtable | ||
| + | | limit=0 | ||
| + | | sep=, | ||
| + | | searchlabel=Click to browse all 10 µm models | ||
| + | }} | ||
| + | == 10 µm Chips == | ||
| + | * Intel | ||
| + | ** {{intel|3000}} | ||
| + | * RCA | ||
| + | ** {{rca|CD4000|CD4000 Series}} | ||
{{expand list}} | {{expand list}} | ||
| − | [[ | + | |
| + | {{stub}} | ||
| + | [[category:lithography]] | ||
Latest revision as of 22:04, 20 May 2018
Semiconductor lithography processes technology
The 10 µm lithography process was the semiconductor process technology used by the major semiconductor companies during the years of 1967 and 1973. This process had an effective channel length of roughly 10 µm between the source and drain (Poly-SI channel implant). The typical wafer size for this process at companies such as Fairchild and TI was 2-inch (51 mm).
Industry[edit]
| Fab |
|---|
| Process Name |
| 1st Production |
| Contacted Gate Pitch |
| Interconnect Pitch |
| Metal Layers |
| Technology |
| Wafer |
| Intel | TI | RCA | Fairchild | National | MIL |
|---|---|---|---|---|---|
| 1970 | 1969 | 1969 | 1969 | ||
| ? nm | ? nm | ? nm | ? nm | ? nm | ? nm |
| ? nm | ? nm | ? nm | ? nm | ? nm | ? nm |
| 2 | 2 | 2 | 2 | ||
| PMOS | PMOS | CMOS | PMOS | PMOS | |
| 51 mm |
10 µm Microprocessors[edit]
This list is incomplete; you can help by expanding it.
Click to browse all 10 µm models
10 µm Chips[edit]
- Intel
- RCA
This list is incomplete; you can help by expanding it.
 |
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |