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Difference between revisions of "130 nm lithography process"
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== References == | == References == | ||
* Tyagi, Sunit, et al. "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects." Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. IEEE, 2000. | * Tyagi, Sunit, et al. "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects." Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. IEEE, 2000. |
Revision as of 21:40, 14 January 2018
The 130 nanometer (130 nm) lithography process is a full node semiconductor manufacturing process following the 150 nm process stopgap. Commercial integrated circuit manufacturing using 130 nm process began in 2001. This technology was replaced by with 110 nm process (HN) in 2003 and 90 nm process (FN) in 2004.
Contents
Industry
Fab |
---|
Process Name |
1st Production |
Type |
Wafer |
Metal Layers |
|
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell (HP) |
SRAM bit cell (HD) |
Intel | TSMC | Samsung | Fujitsu | IBM / Infineon / UMC | Motorola | AMD | NEC | NEC | TI | TI | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
P860 | CS-91 | CMOS 9S | HiPerMOS 7 | ||||||||||||||||||
2001 | 2001 | 2001 | 2002 | 2001 | 2001 | 2002 | 2001 | 2001 | 2001 | ||||||||||||
Bulk | PDSOI | Bulk | |||||||||||||||||||
200 mm | |||||||||||||||||||||
6 | 8 | 8 | 5 | 7 | 6 | 7 | |||||||||||||||
Value | 180 nm Δ | Value | 180 nm Δ | Value | 180 nm Δ | Value | 180 nm Δ | Value | 180 nm Δ | Value | 180 nm Δ | Value | 180 nm Δ | Value | 180 nm Δ | Value | 180 nm Δ | Value | 180 nm Δ | Value | 180 nm Δ |
319 nm | 0.66x | 310 nm | ?x | 350 nm | ?x | ? nm | ?x | 350 nm | ?x | 350 nm | ?x | 350 nm | ?x | ?nm | ?x | ?nm | ?x | ?nm | ?x | ?nm | ?x |
345 nm | 0.69x | 340 nm | ?x | 350 nm | ?x | ? nm | ?x | 320 nm | ?x | 350 nm | ?x | 350 nm | ?x | ?nm | ?x | ?nm | ?x | ?nm | ?x | ?nm | ?x |
2.45 µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x |
2.09 µm² | 0.36x | 2.14 µm² | 0.46x | ? µm² | ?x | 1.98 µm² | 0.47x | 1.8 µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x |
Design Rules
Intel 130nm Design Rules | |||
---|---|---|---|
Layer | Pitch | Thick | Aspect Ratio |
Isolation | 345 nm | 450 nm | - |
Polysilicon | 319 nm | 160 nm | - |
Metal 1 | 293 nm | 280 nm | 1.7 |
Metal 2 | 425 nm | 360 nm | 1.7 |
Metal 3 | 425 nm | 360 nm | 1.7 |
Metal 4 | 718 nm | 570 nm | 1.6 |
Metal 5 | 1.064 µm | 900 nm | 1.7 |
Metal 6 | 1.143 µm | 1.2 µm | 2.1 |
130 nm Microprocessors
- Ambric
- AMD
- Cavium
- HAL (Fujitsu)
- IBM
- Intel
- Intrinsity
- Loongson
- Qualcomm
- SGI
- Sun
- NUDT
This list is incomplete; you can help by expanding it.
130 nm programmable logic devices
- MathStar
This list is incomplete; you can help by expanding it.
130 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- Tyagi, Sunit, et al. "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects." Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. IEEE, 2000.