Revision as of 21:02, 15 March 2017

Semiconductor lithography processes technology

1 nm 2 nm 3 nm 5 nm 7 nm 10 nm 14 nm 16 nm 20 nm 22 nm 28 nm 32 nm 40 nm 45 nm 55 nm 65 nm 80 nm 90 nm 110 nm 130 nm 150 nm 180 nm 220 nm 240 nm 250 nm 280 nm 350 nm 500 nm 600 nm 650 nm 700 nm 750 nm 800 nm 1 µm 1.2 µm 1.3 µm 1.5 µm 2 µm 2.5 µm 3 µm 3.5 µm 5 µm 6 µm 7 µm 8 µm 10 µm 16 µm 20 µm 50 µm

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The 5 nanometer (5 nm) lithography process is a full node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2021 or 2022. The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch.

Initial research

• At the 2016 IEEE International Electron Devices Meeting (IEDM), researchers from CEA-Leti presented a paper detailing the architecture for a possible 5 nm node. The researchers presented their functional vertically stacked gate-all-around (GAA) silicon NW/NS (NanoWire/NanoSheet) MOSFETs. GAA NW transistors are a highly promising candidate to succeed FinFETs as the drive current can be optimized by vertically stacking multiple horizontal nanowires.

Industry

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

5 nm Microprocessors

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5 nm Microarchitectures

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References

• TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017