From WikiChip
Difference between revisions of "28 nm lithography process"
(→Industry) |
(→Industry) |
||
Line 3: | Line 3: | ||
== Industry == | == Industry == | ||
− | + | {{scrolling table/top|style=text-align: right; | first=Fab | |
− | + | | | |
− | { | + | |Contacted Gate Pitch |
+ | |Interconnect Pitch (M1P) | ||
+ | |SRAM bit cell (HD) | ||
+ | |SRAM bit cell (LP) | ||
+ | }} | ||
+ | {{scrolling table/mid}} | ||
|- | |- | ||
− | | | | + | ! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] |
|- | |- | ||
− | + | ! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ | |
|- | |- | ||
− | | | + | | 90 nm || 0.70x || 117 nm || 0.72x |
|- | |- | ||
− | | | + | | 96 nm || 0.82x || ?nm || ?x |
− | | | ||
− | |||
− | |||
− | |||
|- | |- | ||
− | | || | + | | 0.120 µm<sup>2</sup> || ?x || 0.127 µm<sup>2</sup> || 0.52x |
|- | |- | ||
− | | | + | | || || 0.155 µm<sup>2</sup> || |
− | + | {{scrolling table/end}} | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== 28 nm Microprocessors == | == 28 nm Microprocessors == |
Revision as of 04:20, 24 April 2016
The 28 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.
Industry
Fab |
---|
|
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell (HD) |
SRAM bit cell (LP) |
Samsung | TSMC | ||
---|---|---|---|
Value | 40 nm Δ | Value | 40 nm Δ |
90 nm | 0.70x | 117 nm | 0.72x |
96 nm | 0.82x | ?nm | ?x |
0.120 µm2 | ?x | 0.127 µm2 | 0.52x |
0.155 µm2 |
28 nm Microprocessors
This list is incomplete; you can help by expanding it.
28 nm System on Chips
- Intel
This list is incomplete; you can help by expanding it.