Semiconductor & Computer Engineering
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Difference between revisions of "40 nm lithography process"
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| [[SRAM]] bit cell || ? µm<sup>2</sup> || ?x | | [[SRAM]] bit cell || ? µm<sup>2</sup> || ?x | ||
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| + | === Toshiba / NEC === | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | | || Measurement | ||
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| + | | Contacted Gate Pitch || 168 nm | ||
| + | |- | ||
| + | | Interconnect Pitch (M1P) || ? nm | ||
| + | |- | ||
| + | | [[SRAM]] bit cell || 0.195 µm<sup>2</sup> | ||
|} | |} | ||
Revision as of 23:17, 23 April 2016
Semiconductor lithography processes technology
The 40 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 45 nm and 32 nm processes. Commercial integrated circuit manufacturing using 40 nm process began in 2008 by leading semiconductor companies such as TSMC. This technology superseded by commercial 32 nm process by 2010.
Industry
Samsung
| Measurement | Scaling from 65 nm | |
| Contacted Gate Pitch | 129 nm | 0.65x |
| Interconnect Pitch (M1P) | 117 nm | 0.65x |
| SRAM bit cell | ? µm2 | ?x |
Toshiba / NEC
| Measurement | |
| Contacted Gate Pitch | 168 nm |
| Interconnect Pitch (M1P) | ? nm |
| SRAM bit cell | 0.195 µm2 |
40 nm Microprocessors
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40 nm System on Chips
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