From WikiChip
Difference between revisions of "90 nm lithography process"
(→Industry) |
|||
(20 intermediate revisions by 4 users not shown) | |||
Line 1: | Line 1: | ||
{{lithography processes}} | {{lithography processes}} | ||
− | The '''90 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[110 nm lithography process|110 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 90 nm process began in 2003. This technology was superseded by the [[80 nm lithography process|80 nm process]] (HN) / [[65 nm lithography process|65 nm process]] (FN) in 2006. | + | The '''90 nanometer (90 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[110 nm lithography process|110 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 90 nm process began in 2003. This technology was superseded by the [[80 nm lithography process|80 nm process]] (HN) / [[65 nm lithography process|65 nm process]] (FN) in 2006. |
== Industry == | == Industry == | ||
+ | Introduced in late 2002, Intel's 90 nm process became the first volume production to introduce [[strained silicon]] transistors. | ||
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
|Process Name | |Process Name | ||
Line 8: | Line 9: | ||
|Type | |Type | ||
|Wafer | |Wafer | ||
+ | |Metal Layers | ||
| | | | ||
|Contacted Gate Pitch | |Contacted Gate Pitch | ||
Line 16: | Line 18: | ||
{{scrolling table/mid}} | {{scrolling table/mid}} | ||
|- | |- | ||
− | ! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Fujitsu]] || colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] / [[Chartered]] | + | ! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Fujitsu]] || colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] / [[Chartered]] !! colspan="2" | [[Motorola]] !! colspan="2" | [[TI]] |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | P1262 || colspan="2" | || colspan="2" | || colspan="2" | CS-100 / CS-101 || colspan="2" | | + | | colspan="2" | P1262 || colspan="2" | || colspan="2" | || colspan="2" | CS-100 / CS-101 || colspan="2" | || colspan="2" | HiPerMOS 8 || colspan="2" | |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | 2002 || colspan="2" | 2003 || colspan="2" | 2003 || colspan="2" | 2004 || colspan="2" | 2003 | + | | colspan="2" | 2002 || colspan="2" | 2003 || colspan="2" | 2003 || colspan="2" | 2004 || colspan="2" | 2003 || colspan="2" | 2004 || colspan="2" | 2005 |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="8" | Bulk || colspan="2" | | + | | colspan="8" | Bulk || colspan="4" | PDSOI || colspan="2" | Bulk |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="10" | | + | | colspan="14" | 300mm |
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | 7 || colspan="2" | || colspan="2" | || colspan="2" | 10 || colspan="2" | || colspan="2" | || colspan="2" | 9 | ||
|- | |- | ||
− | ! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ | + | ! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ |
|- | |- | ||
− | | 260 nm || 0.82x || 240 nm || 0.77x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x | + | | 260 nm || 0.82x || 240 nm || 0.77x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x |
|- | |- | ||
− | | 220 nm || 0.63x || 240 nm || 0.71x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x | + | | 220 nm || 0.63x || 240 nm || 0.71x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x |
|- | |- | ||
− | | 1.0 | + | | 1.0 µm² || 0.50x || 0.999 µm² || 0.47x || 0.999 µm² || ?x || 1.07 µm² || 0.54x || 0.999 µm² || ?x || ? µm² || ?x || ? µm² || ?x |
|- | |- | ||
− | | || || || || || || || || 0.19 | + | | || || || || 0.275 µm² || || || || 0.19 µm² || ?x || || || || |
{{scrolling table/end}} | {{scrolling table/end}} | ||
== 90 nm Microprocessors== | == 90 nm Microprocessors== | ||
− | {{ | + | * AMD |
− | + | ** {{amd|Athlon 64}} | |
− | + | ** {{amd|Athlon 64 X2}} | |
+ | ** {{amd|FX}} | ||
+ | ** {{amd|Opteron}} | ||
+ | ** {{amd|Turion 64}} | ||
+ | ** {{amd|Turion 64 X2}} | ||
+ | * Cavium | ||
+ | ** {{cavium|OCTEON Plus}} | ||
+ | * HAL (Fujitsu) | ||
+ | ** {{hal|SPARC64 V}} | ||
+ | * IBM | ||
+ | ** {{ibm|PowerPC 970}} | ||
+ | * Loongson | ||
+ | ** {{loongson|Godson 2}} | ||
+ | * Qualcomm | ||
+ | ** {{qualcomm|MSM6xxx}} | ||
+ | * Sun | ||
+ | ** {{sun|UltraSPARC T1}} | ||
* Intel | * Intel | ||
** {{intel|Pentium 4 Extreme Edition}} | ** {{intel|Pentium 4 Extreme Edition}} | ||
** {{intel|Pentium M}} | ** {{intel|Pentium M}} | ||
** {{intel|Pentium D}} | ** {{intel|Pentium D}} | ||
+ | ** {{intel|EP80579}} | ||
+ | |||
+ | |||
{{expand list}} | {{expand list}} | ||
== 90 nm Microarchitectures == | == 90 nm Microarchitectures == | ||
+ | * AMD | ||
+ | ** {{amd|K8|l=arch}} | ||
+ | * ARM | ||
+ | ** {{armh|ARM7|l=arch}} | ||
+ | * IBM | ||
+ | ** {{ibm|z9|l=arch}} | ||
+ | * Intel | ||
+ | ** {{intel|Pentium M|l=arch}} | ||
+ | * VIA Technologies | ||
+ | ** {{via|Esther|l=arch}} | ||
{{expand list}} | {{expand list}} | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:samsung foundry - 45, 65, 90 (August, 2007).pdf|Samsung foundry - 45 nm, 65 nm, 90 nm guide (August, 2007)]] | ||
+ | |||
+ | [[category:lithography]] |
Revision as of 05:56, 20 July 2018
The 90 nanometer (90 nm) lithography process is a full node semiconductor manufacturing process following the 110 nm process stopgap. Commercial integrated circuit manufacturing using 90 nm process began in 2003. This technology was superseded by the 80 nm process (HN) / 65 nm process (FN) in 2006.
Industry
Introduced in late 2002, Intel's 90 nm process became the first volume production to introduce strained silicon transistors.
Fab |
---|
Process Name |
1st Production |
Type |
Wafer |
Metal Layers |
|
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell |
DRAM bit cell |
Intel | TSMC | Samsung | Fujitsu | IBM / Toshiba / Sony / AMD / Chartered | Motorola | TI | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
P1262 | CS-100 / CS-101 | HiPerMOS 8 | |||||||||||
2002 | 2003 | 2003 | 2004 | 2003 | 2004 | 2005 | |||||||
Bulk | PDSOI | Bulk | |||||||||||
300mm | |||||||||||||
7 | 10 | 9 | |||||||||||
Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ |
260 nm | 0.82x | 240 nm | 0.77x | 245 nm | 0.70x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
220 nm | 0.63x | 240 nm | 0.71x | 245 nm | 0.70x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
1.0 µm² | 0.50x | 0.999 µm² | 0.47x | 0.999 µm² | ?x | 1.07 µm² | 0.54x | 0.999 µm² | ?x | ? µm² | ?x | ? µm² | ?x |
0.275 µm² | 0.19 µm² | ?x |
90 nm Microprocessors
- AMD
- Cavium
- HAL (Fujitsu)
- IBM
- Loongson
- Qualcomm
- Sun
- Intel
This list is incomplete; you can help by expanding it.
90 nm Microarchitectures
This list is incomplete; you can help by expanding it.