Semiconductor & Computer Engineering
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| Line 35: | Line 35: | ||
| 0.064 µm<sup>2</sup> || ?x || 0.064 µm<sup>2</sup> || ?x | | 0.064 µm<sup>2</sup> || ?x || 0.064 µm<sup>2</sup> || ?x | ||
{{scrolling table/end}} | {{scrolling table/end}} | ||
| + | === Design Rules === | ||
| + | {| class="wikitable collapsible collapsed" | ||
| + | |- | ||
| + | ! colspan="3" | Intel 14nm Design Rules | ||
| + | |- | ||
| + | ! Layer !! Pitch !! Scale Factor | ||
| + | |- | ||
| + | | Fin || 42 nm || 0.70 | ||
| + | |- | ||
| + | | Contacted Gate Pitch || 70 nm || 0.78 | ||
| + | |- | ||
| + | | Metal 0 || 56 || - | ||
| + | |- | ||
| + | | Metal 1 || 70 || 0.78 | ||
| + | |- | ||
| + | | Metal 2 || 52 || 0.65 | ||
| + | |} | ||
== 14 nm Microprocessors== | == 14 nm Microprocessors== | ||
| Line 56: | Line 73: | ||
** {{intel|Broadwell}} | ** {{intel|Broadwell}} | ||
** {{intel|Skylake}} | ** {{intel|Skylake}} | ||
| + | |||
| + | == Documents == | ||
| + | * [http://www.intel.com/content/dam/www/public/us/en/documents/pdf/foundry/intel-14nm-iedm-2014-presentation.pdf A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size], 15-17 Dec. 2014; 10.1109/IEDM.2014.7046976 | ||
{{expand list}} | {{expand list}} | ||
[[Category:Lithography]] | [[Category:Lithography]] | ||
Revision as of 02:01, 24 April 2016
Semiconductor lithography processes technology
The 14 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 16 nm and 10 nm processes. As is the case with all recent process nodes, while the term "14 nm" is used by a number of companies, the exact feature sizes various wildly from one manufacturer to another. Commercial integrated circuit manufacturing using 14 nm process began in 2014. This technology is set to be replaced with 10 nm process in 2017.
Contents
Industry
14 nm became Intel's 2nd generation finFET transistors. This process became Samsungs' and GlobalFoundries first generation of finFet-based transistors. Intel uses TiN pMOS / TiAlN nMOS while Samsung uses TiN pMOS / TiAIC nMOS as work function metals.
| Fab |
|---|
| |
| Fin Pitch |
| Fin Width |
| Fin Height |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell (HP) |
| SRAM bit cell (HD) |
| Intel | Samsung | GlobalFoundries | |||
|---|---|---|---|---|---|
| Value | 22 nm Δ | Value | 20 nm Δ | Value | 20 nm Δ |
| 42 nm | 0.70x | 48 nm | - | 48 nm | - |
| 8 nm | 1.00x | 8 nm | - | 8 nm | - |
| 42 nm | 1.24x | ~38 nm | - | ~38 nm | |
| 70 nm | 0.78x | 78 nm | 1.22x | 78 nm | 1.22x |
| 52 nm | 0.65x | 64 nm | 1.00x | 64 nm | 1.00x |
| 0.0588 µm2 | 0.54x | 0.08 µm2 | ?x | 0.08 µm2 | ?x |
| 0.064 µm2 | ?x | 0.064 µm2 | ?x | ||
Design Rules
| Intel 14nm Design Rules | ||
|---|---|---|
| Layer | Pitch | Scale Factor |
| Fin | 42 nm | 0.70 |
| Contacted Gate Pitch | 70 nm | 0.78 |
| Metal 0 | 56 | - |
| Metal 1 | 70 | 0.78 |
| Metal 2 | 52 | 0.65 |
14 nm Microprocessors
- Intel
This list is incomplete; you can help by expanding it.
14 nm System on Chips
This list is incomplete; you can help by expanding it.
14 nm Microarchitectures
Documents
- A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size, 15-17 Dec. 2014; 10.1109/IEDM.2014.7046976
This list is incomplete; you can help by expanding it.
