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Difference between revisions of "14 nm lithography process"

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| colspan="2" | P1272 || colspan="2" |  || colspan="2" |  || colspan="2" |
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| colspan="2" | 2014 || colspan="2" | 2015 || colspan="2" | 2015 || colspan="2" | 2015
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| colspan="6" | Bulk || colspan="2" | PDSOI
 
| colspan="6" | Bulk || colspan="2" | PDSOI
 
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Revision as of 19:11, 24 April 2016

The 14 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 16 nm and 10 nm processes. As is the case with all recent process nodes, while the term "14 nm" is used by a number of companies, the exact feature sizes various wildly from one manufacturer to another. Commercial integrated circuit manufacturing using 14 nm process began in 2014. This technology is set to be replaced with 10 nm process in 2017.

Industry

14 nm became Intel's 2nd generation finFET transistors. This process became Samsungs' and GlobalFoundries first generation of finFet-based transistors. Intel uses TiN pMOS / TiAlN nMOS while Samsung uses TiN pMOS / TiAIC nMOS as work function metals.

Fab
Process Name​
1st Production​
Type​
 ​
Fin Pitch​
Fin Width​
Fin Height​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HP)​
SRAM bit cell (HD)
Intel Samsung GlobalFoundries IBM
P1272
2014 2015 2015 2015
Bulk PDSOI
Value 22 nm Δ Value 20 nm Δ Value 20 nm Δ Value 22 nm Δ
42 nm 0.70x 48 nm N/A 48 nm N/A 42 nm N/A
8 nm 1.00x 8 nm 8 nm 10 nm
42 nm 1.24x ~38 nm ~38 nm 25 nm
70 nm 0.78x 78 nm 1.22x 78 nm 1.22x 80 nm 0.80x
52 nm 0.65x 64 nm 1.00x 64 nm 1.00x 64 nm 0.80x
0.0588 µm2 0.54x 0.08 µm2  ?x 0.08 µm2  ?x  ? µm2  ?x
0.064 µm2  ?x 0.064 µm2  ?x  ? µm2  ?x

Design Rules

14 nm Microprocessors

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14 nm System on Chips

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14 nm Microarchitectures

Documents

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