From WikiChip
3 nm lithography process
The 3.5 nanometer (3.5 nm) or 35 Å lithography process is a full node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3.5 nm process is set to begin sometimes around 2024 or 2025. The term "3.5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch.
Industry
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Intel | TSMC | GlobalFoundries | Samsung | ||||
---|---|---|---|---|---|---|---|
P1280? (CPU), P1281? (SoC) | |||||||
EUV | EUV | EUV | EUV | ||||
SE | SE | SE | SE | ||||
Bulk | Bulk | Bulk | Bulk | ||||
300 nm | 300 nm | 300 nm | 300 nm | ||||
GAA | |||||||
Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ |
N/A | |||||||
3.5 nm Microprocessors
This list is incomplete; you can help by expanding it.
3.5 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017