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28 nm lithography process
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The 28 nanometer (28 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.

Industry

 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
TSMC Common Platform Alliance
The 'Common Platform Alliance is a joint collaboration between IBM, Samsung, GlobalFoundries, Toshiba, NEC, STMicroelectronics, Infineon Technologies, Chartered Semiconductor Manufacturing
  28LP/28LPP/28SLP
  2
   
   
   
Bulk Bulk
300 mm 300 mm
Planar Planar
  1 V
10  
Value 32 nm Δ Value 32 nm Δ
       
    113.4 nm  
    90 nm  
    0.152 µm²  
    0.120 µm²  
    0.197 µm²  
       

28 nm Microprocessors

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28 nm Microarchitectures

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References

  • Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009.
  • Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
  • James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.
  • Samsung foundry solution for 32 & 28 nm