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From WikiChip
2 µm lithography process
Semiconductor lithography processes technology |
|
The 2 µm lithography process was the semiconductor process technology used by the some semiconductor companies in the mid to late 1980s. By the mid 80s this process was replaced by 1.5 µm, 1.3 µm, and 1.2 µm processes.
Industry
Fab |
---|
Process Name |
1st Production |
Voltage |
|
Gate Length |
Interconnect Pitch (M1P) |
SRAM bit cell |
Intel | Intel | Toshiba | STMicro | Motorola | TI | AMD | Hitachi | |
---|---|---|---|---|---|---|---|---|
P414.1 (HMOS-II) | P421.X (HMOS-E) | BCD-Offline | Hi-CMOS II | |||||
1980 | 1980 | 1986 | 1992 | 1982 | ||||
5 V | ||||||||
Value | Value | Value | Value | Value | Value | Value | Value | 65 nm Δ |
? µm | ? µm | ? µm | ? µm | ? µm | ? µm | ? µm | 2 µm | 0.67x |
? µm | ? µm | ? µm | ? µm | ? µm | ? µm | ? µm | 3 µm | 1x |
? µm² | ? µm² | ? µm² | ? µm² | ? µm² | ? µm² | ? µm² | 303.8 µm² | 0.34x |
Microprocessors
This list is incomplete; you can help by expanding it.
References
- Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
- Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.