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10 µm lithography process
Revision as of 07:33, 27 April 2016 by Inject (talk | contribs) (Industry)

The 10 µm lithography process was the semiconductor process technology used by the major semiconductor companies during the years of 1967 and 1973. The typical wafer size for this process at companies such as Fairchild and TI were 1.5 inch (38 mm).

Industry

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch​
Metal Layers​
Technology​
Wafer
Intel TI RCA Fairchild National
 
1970 1969 1969
 ? nm  ? nm  ? nm  ? nm  ? nm
 ? nm  ? nm  ? nm  ? nm  ? nm
2 2 2 2
PMOS PMOS CMOS PMOS PMOS
51 mm

10 µm Microprocessors

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10 µm Chips

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