The 250 nm lithography process is a full node semiconductor manufacturing process following the 350 nm process node. Commercial integrated circuit manufacturing using 250 nm process began in 1997 and was eventually replaced by 180 nm by 1999.

Industry

The 0.25 µm-based process entered production at Intel in 1997. Intel original 0.25 micron process was named P856 or Process 856. A second process, named P856.5, was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm², 6T SRAM. The process used 200 mm wafers, SiO₂ dielectric and polysilicon electode. It used Al inter-connects and an Si channels.

Fab
Type​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell

Intel
Value	350 nm Δ
? nm	?x
608 nm	0.69x
10.26 µm2	0.57x

Design Rules

Intel 0.25 micron Design Rules (P856)
Layer	Pitch	Thick	Aspect Ratio
Isolation	? nm	? nm	-
Polysilicon	? nm	? nm	-
Metal 1	640 nm	480 nm	1.6
Metal 2	930 nm	900 nm	2.0
Metal 3	930 nm	900 nm	2.0
Metal 4	1.60 µm	1.325 µm	1.7
Metal 5	2.56 µm	1.900 nm	1.6

Intel 0.25 %5 shrink micron Design Rules (P856.5)
Layer	Pitch	Thick	Aspect Ratio
Isolation	? nm	? nm	-
Polysilicon	? nm	? nm	-
Metal 1	608 nm	480 nm	1.6
Metal 2	882 nm	900 nm	2.0
Metal 3	882 nm	900 nm	2.0
Metal 4	1.520 µm	1.325 µm	1.7
Metal 5	2.432 µm	1.900 nm	1.6

250 nm Microprocessors

• Intel
  • Pentium MMX, 200-300 MHz September, 1997
  • Pentium II, 333-450 MHz, January 1998
  • Pentium II Notebook, 233-300 MHz, April 1998
  • Celeron, 200-300 MHz, April 1998
  • Celeron, 300-533 MHz, August 1998
  • Celeron Notebook, 266-466 MHz, January 1999
  • Pentium III, 450-600 MHz, February 1999
• MIPS
  • R10000, 1997, fab'ed by NEC

This list is incomplete; you can help by expanding it.

250 nm Microarchitectures

This list is incomplete; you can help by expanding it.