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Semiconductor lithography processes technology

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The 7 nanometer (7 nm) lithography process is a technology node semiconductor manufacturing process following the 10 nm process node. The term "7 nm" is simply a commercial name for a generation of a certain size and its technology and does not represent any geometry of a transistor. Commercial mass production of integrated circuit using 7 nm process is set to begin sometimes in 2019 or 2020. This technology will be replaced by 5 nm process around 2022.

Industry

Only four semiconductor foundries are able to develop the advanced 7nm: Intel, Samsung, TSMC, and GlobalFoundries.

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Intel

On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel's 7 nm node has entered development phase and that the company's research focuses on the 5 nm and 3 nm nodes. Intel has been maintaining the details of their 7 nm node secrete for now. CEO Brian Krzanich mentioned a 2020 timeframe in an investor conference in June.

GlobalFoundries

On May 30 2017, GlobalFoundries Senior Vice President and head of CMOS Business Unit, Gregg Bartlett, announced their updated roadmap. Instead of EUV, the company will use multiple patterning 193i for their 7 nm node. The company is planning on first tape-out in the 2nd half of 2018 with mass production to begin in 2019. Bartlett noted that GF will switch to EUVL when it's ready.

TSMC

In ISSCC 2017, the memory group at TSMC detailed their test 256 MiB SRAM chip which featured a 42.64 mm² die. The chip is manufactured on TSMC's 7nm HK-MG FinFET process using 4P4E LELELELE patterning technique. The over die is 0.34x smaller than their 16 nm process version.

TSMC will introduce a second improved process called 7nm+, which will introduce some layers processed with EUVL. This will improve yields and reduce fab cycle times. The 7nm+ process will deliver improved power consumption and between 15-20% area scaling over their first generation 7nm process.

TSMC 256 Mib SRAM demo 7 nm wafer
Technology 7 nm HK-MG FinFET Metal scheme 1 Poly / 7 Metal Supply voltage 0.75 V (core) 1.8 V (i/o) Bit cell size 0.027 µm² macro configs 4096x32 MUX16 258 bits/BL 272 bits/WL Capacity 256 Mib Test Features Row/Column Redundancy Programmable E-fuse Die Size 5903 µm x 7223 µm = 42.64 mm²

Samsung

Samsung will use EUVL for their 7nm node and thus will be the first to introduce this new technology after more than a decade of development. On May 24 2017, Samsung released a press release of their updated roadmap. Due to delays in the introduction of EUVL, Samsung will introduce a new process called 8nm LPP, to bridge the gap between 10nm and 7nm. The process will be manufactured without the use of EUVL and will feature a slightly relaxed transistor size.

7 nm Microprocessors

• PEZY
  • PEZY-SC3
• MediaTek
  • Helio

This list is incomplete; you can help by expanding it.

7 nm Microarchitectures

• AMD
  • Zen 2
  • Zen 3

See also

• Intel proces technology history

References

• Chang, Jonathan, et al. "12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V MIN applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.
• Standaert, T., et al. "BEOL process integration for the 7 nm technology node." Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2016 IEEE International. IEEE, 2016.
• Samsung/GlobalFoundries, IEEE International Electron Devices Meeting (IEDM) 2016