Revision as of 13:54, 1 June 2017

Semiconductor lithography processes technology

1 nm • 18A 2 nm • 3 nm 5 nm • 7 nm 10 nm • 12 nm 14 nm • 16 nm 20 nm • 22 nm 28 nm • 32 nm 40 nm • 45 nm 55 nm • 65 nm 80 nm • 90 nm 110 nm • 130 nm 150 nm • 180 nm 220 nm • 240 nm 250 nm • 280 nm 350 nm • 500 nm 600 nm • 650 nm 700 nm • 750 nm 800 nm 1 µm • 1.2 µm 1.3 µm • 1.5 µm 2 µm • 2.5 µm 3 µm • 3.5 µm 5 µm • 6 µm 7 µm • 8 µm 10 µm • 16 µm 20 µm • 50 µm

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The 3.5 nanometer (3.5 nm) or 35 Å lithography process is a full node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3.5 nm process is set to begin sometimes around 2024 or 2025. The term "3.5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch.

Industry

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Samsung

On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.

3.5 nm Microprocessors

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3.5 nm Microarchitectures

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References

• Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017