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Difference between revisions of "5 µm lithography process"

(5µm Microprocessors)
(Industry)
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== Industry ==
 
== Industry ==
HP's ''NMOS II'' process as the name implied was a second generation nMOD process which was a shrink of their previous generation [[7 µm]] nMOS also developed by [[HP]]'s Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the ''NMOS III'' using a [[1.5 µm process]]. While they succeeded in doubling the density and more than ten-folding the speed, the complexity of the chip still required them to fabricate it on 3 seperate dies and package them together.
+
HP's ''NMOS II'' was a second generation nMOD process which was a shrink of their previous generation [[7 µm]] nMOS also developed by [[HP]]'s Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the ''NMOS III'' using a [[1.5 µm process]]. While they succeeded in doubling the density and more than ten-folding the speed, the complexity of the chip still required them to fabricate it on 3 separate dies and package them together. Intel introduced their {{intel|2116}} in 1976, the first 16 Kib DRAM which was also implemented using 5 micron design rules.
{{scrolling table/top|style=text-align: right; | first=Fab
+
 
  |Process Name
+
{{#invoke:process nodes
  |1st Production
+
| compare
  |Contacted Gate Pitch
+
| fab 1 name link  = intel
  |Interconnect Pitch
+
| fab 1 name        = Intel
  |Metal Layers
+
| fab 1 proc name  =
  |Technology
+
| fab 1 date        = 1976
  |Wafer
+
| fab 1 wafer.type  = Bulk
 +
| fab 1 wafer.size  = 51 mm
 +
| fab 1 xtor.tech  = nMOS
 +
| fab 1 xtor.type  = Planar
 +
| fab 1 xtor.volt  = 5 V
 +
| fab 1 layers      = 1, 2
 +
| fab 1 diff from  = [[8 µm]] Δ
 +
| fab 1 xtor.lg    = 5 µm
 +
| fab 1 xtor.lgΔ    = 0.63x
 +
| fab 1 xtor.cpp    =
 +
| fab 1 xtor.cppΔ  =
 +
| fab 1 xtor.mmp    =
 +
| fab 1 xtor.mmpΔ  =
 +
| fab 1 sram.hp    =  
 +
| fab 1 sram.hpΔ    =
 +
| fab 1 sram.hd    = 435 µm²
 +
| fab 1 sram.hdΔ    = 0.34x
 +
| fab 1 sram.lv    =
 +
| fab 1 sram.lvΔ    =
 +
| fab 1 dram.edram  =
 +
| fab 1 dram.edramΔ =
 +
 
 +
| fab 2 name link  = hp
 +
| fab 2 name        = HP
 +
| fab 2 proc name  = NMOS II
 +
| fab 2 date        = 1973
 +
| fab 2 wafer.type  = Bulk
 +
| fab 2 wafer.size  = 51 mm
 +
| fab 2 xtor.tech  = nMOS
 +
| fab 2 xtor.type  = Planar
 +
| fab 2 xtor.volt  = 5 V
 +
| fab 2 layers      =
 +
| fab 2 diff from  = [[7 µm]] Δ
 +
| fab 2 xtor.lg    = 5 µm
 +
| fab 2 xtor.lgΔ    = 0.71x
 +
| fab 2 xtor.cpp    =
 +
| fab 2 xtor.cppΔ  =
 +
| fab 2 xtor.mmp    =
 +
| fab 2 xtor.mmpΔ  =
 +
| fab 2 sram.hp    =  
 +
  | fab 2 sram.hpΔ    =
 +
  | fab 2 sram.hd    =
 +
  | fab 2 sram.hdΔ    =
 +
  | fab 2 sram.lv    =
 +
  | fab 2 sram.lvΔ    =
 +
  | fab 2 dram.edram  =
 +
  | fab 2 dram.edramΔ =
 
}}
 
}}
{{scrolling table/mid}}
 
|-
 
! [[HP]]
 
|- style="text-align: center;"
 
| NMOS II
 
|- style="text-align: center;"
 
| 1973
 
|-
 
| ? nm
 
|-
 
| ? nm
 
|-
 
|  
 
|-
 
| nMOS
 
|-
 
|  51 mm
 
{{scrolling table/end}}
 
  
 
== 5µm Microprocessors ==
 
== 5µm Microprocessors ==

Revision as of 17:33, 8 April 2017

The 5μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s. This process was later superseded by 3 µm, 2 µm, and 1.5 µm processes.

Industry

HP's NMOS II was a second generation nMOD process which was a shrink of their previous generation 7 µm nMOS also developed by HP's Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the NMOS III using a 1.5 µm process. While they succeeded in doubling the density and more than ten-folding the speed, the complexity of the chip still required them to fabricate it on 3 separate dies and package them together. Intel introduced their 2116 in 1976, the first 16 Kib DRAM which was also implemented using 5 micron design rules.

Foundry
Process Name
1st Production
WaferType
Size
TransistorTechnology
Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcellHigh-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcelleDRAM
IntelHP
 NMOS II
19761973
BulkBulk
51 mm51 mm
nMOSnMOS
PlanarPlanar
5 V5 V
1, 2
Value8 µm ΔValue7 µm Δ
5 µm0.63x5 µm0.71x
    
    
    
435 µm²0.34x  
    
    

5µm Microprocessors


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