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14 nm became [[Intel]]'s 2nd generation finFET transistors. This process became Samsungs' and GlobalFoundries first generation of finFet-based transistors. Intel uses TiN pMOS / TiAlN nMOS while Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Intel makes use of [[Self-Aligned Double Patterning]] (SADP) with 193 nm immersion lithography at critical patterning layers.  
 
14 nm became [[Intel]]'s 2nd generation finFET transistors. This process became Samsungs' and GlobalFoundries first generation of finFet-based transistors. Intel uses TiN pMOS / TiAlN nMOS while Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Intel makes use of [[Self-Aligned Double Patterning]] (SADP) with 193 nm immersion lithography at critical patterning layers.  
  
−
{{scrolling table/top|style=text-align: right; | first=Fab
+
{{finfet nodes comp
−
  |Process Name
+
<!-- Intel -->
−
  |1st Production
+
| process 1 fab          = [[Intel]]
−
  |Transistor
+
| process 1 name        = P1272 (CPU) / P1273 (SoC)
−
  |Type
+
| process 1 date        = 2014
−
  |Wafer
+
| process 1 lith        = &nbsp;
−
  |&nbsp;
+
| process 1 immersion    = &nbsp;
−
  |Fin Pitch
+
| process 1 exposure    = &nbsp;
−
  |Fin Width
+
| process 1 wafer type  = Bulk
−
  |Fin Height
+
| process 1 wafer size  = 300 mm
−
  |Gate Length
+
| process 1 transistor  = FinFET
−
  |Contacted Gate Pitch
+
| process 1 volt        = &nbsp;
−
  |Interconnect Pitch (M1P)
+
| process 1 delta from  = [[22 nm]] Δ
−
  |SRAM bit cell (HP)
+
| process 1 fin pitch    = 42 nm
−
  |SRAM bit cell (HD)
+
| process 1 fin pitch Δ  = 0.70x
−
  |DRAM bit cell
+
| process 1 fin width    = 8 nm
 +
| process 1 fin width Δ  = 1.00x
 +
| process 1 fin height  = 42 nm
 +
| process 1 fin height Δ = 1.24x
 +
| process 1 gate len    = 20 nm
 +
| process 1 gate len Δ  = 0.77x
 +
| process 1 cpp          = 70 nm
 +
| process 1 cpp Δ        = 0.78x
 +
| process 1 mmp          = 52 nm
 +
| process 1 mmp Δ        = 0.65x
 +
| process 1 sram hp      = 0.0706 µm²
 +
| process 1 sram hp Δ    = &nbsp;
 +
| process 1 sram hd      = 0.0499 µm²
 +
| process 1 sram hd Δ    = &nbsp;
 +
| process 1 sram lv      = 0.0588 µm²
 +
| process 1 sram lv Δ    = &nbsp;
 +
| process 1 dram        = &nbsp;
 +
| process 1 dram Δ      = &nbsp;
 +
<!-- Samsung -->
 +
| process 2 fab          = [[Samsung]]
 +
| process 2 name        = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info>
 +
| process 2 date        = &nbsp;
 +
| process 2 lith        = &nbsp;
 +
| process 2 immersion    = &nbsp;
 +
| process 2 exposure    = &nbsp;
 +
| process 2 wafer type  = Bulk
 +
| process 2 wafer size  = 300 mm
 +
| process 2 transistor  = FinFET
 +
| process 2 volt        = &nbsp;
 +
| process 2 delta from  = [[20 nm]] Δ
 +
| process 2 fin pitch    = &nbsp;
 +
| process 2 fin pitch Δ  = &nbsp;
 +
| process 2 fin width    = &nbsp;
 +
| process 2 fin width Δ  = &nbsp;
 +
| process 2 fin height  = &nbsp;
 +
| process 2 fin height Δ = &nbsp;
 +
| process 2 gate len    = &nbsp;
 +
| process 2 gate len Δ  = &nbsp;
 +
| process 2 cpp          = &nbsp;
 +
| process 2 cpp Δ        = &nbsp;
 +
| process 2 mmp          = &nbsp;
 +
| process 2 mmp Δ        = &nbsp;
 +
| process 2 sram hp      = &nbsp;
 +
| process 2 sram hp Δ    = &nbsp;
 +
| process 2 sram hd      = &nbsp;
 +
| process 2 sram hd Δ    = &nbsp;
 +
| process 2 sram lv      = &nbsp;
 +
| process 2 sram lv Δ    = &nbsp;
 +
| process 2 dram        = &nbsp;
 +
| process 2 dram Δ      = &nbsp;
 +
<!-- GlobalFoundries -->
 +
| process 3 fab          = [[GlobalFoundries]]
 +
| process 3 name        = 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>
 +
| process 3 date        = &nbsp;
 +
| process 3 lith        = &nbsp;
 +
| process 3 immersion    = &nbsp;
 +
| process 3 exposure    = &nbsp;
 +
| process 3 wafer type  = Bulk
 +
| process 3 wafer size  = 300 mm
 +
| process 3 transistor  = FinFET
 +
| process 3 volt        = &nbsp;
 +
| process 3 delta from  = [[20 nm]] Δ
 +
| process 3 fin pitch    = &nbsp;
 +
| process 3 fin pitch Δ  = &nbsp;
 +
| process 3 fin width    = &nbsp;
 +
| process 3 fin width Δ  = &nbsp;
 +
| process 3 fin height  = &nbsp;
 +
| process 3 fin height Δ = &nbsp;
 +
| process 3 gate len    = &nbsp;
 +
| process 3 gate len Δ  = &nbsp;
 +
| process 3 cpp          = &nbsp;
 +
| process 3 cpp Δ        = &nbsp;
 +
| process 3 mmp          = &nbsp;
 +
| process 3 mmp Δ        = &nbsp;
 +
| process 3 sram hp      = &nbsp;
 +
| process 3 sram hp Δ    = &nbsp;
 +
| process 3 sram hd      = &nbsp;
 +
| process 3 sram hd Δ    = &nbsp;
 +
| process 3 sram lv      = &nbsp;
 +
| process 3 sram lv Δ    = &nbsp;
 +
| process 3 dram        = &nbsp;
 +
| process 3 dram Δ      = &nbsp;
 +
<!-- IBM -->
 +
| process 4 fab          = [[IBM]]
 +
| process 4 name        = &nbsp;
 +
| process 4 date        = &nbsp;
 +
| process 4 lith        = &nbsp;
 +
| process 4 immersion    = &nbsp;
 +
| process 4 exposure    = &nbsp;
 +
| process 4 wafer type  = SOI
 +
| process 4 wafer size  = 300 mm
 +
| process 4 transistor  = FinFET
 +
| process 4 volt        = &nbsp;
 +
| process 4 delta from  = [[22 nm]] Δ
 +
| process 4 fin pitch    = &nbsp;
 +
| process 4 fin pitch Δ  = &nbsp;
 +
| process 4 fin width    = &nbsp;
 +
| process 4 fin width Δ  = &nbsp;
 +
  | process 4 fin height  = &nbsp;
 +
  | process 4 fin height Δ = &nbsp;
 +
  | process 4 gate len    = &nbsp;
 +
  | process 4 gate len Δ  = &nbsp;
 +
  | process 4 cpp          = &nbsp;
 +
  | process 4 cpp Δ        = &nbsp;
 +
  | process 4 mmp          = &nbsp;
 +
  | process 4 mmp Δ        = &nbsp;
 +
  | process 4 sram hp      = &nbsp;
 +
  | process 4 sram hp Δ    = &nbsp;
 +
  | process 4 sram hd      = &nbsp;
 +
  | process 4 sram hd Δ    = &nbsp;
 +
| process 4 sram lv      = &nbsp;
 +
| process 4 sram lv Δ    = &nbsp;
 +
| process 4 dram        = &nbsp;
 +
| process 4 dram Δ      = &nbsp;
 +
<!-- UMC -->
 +
| process 5 fab          = [[UMC]]
 +
| process 5 name        = &nbsp;
 +
| process 5 date        = &nbsp;
 +
| process 5 lith        = &nbsp;
 +
| process 5 immersion    = &nbsp;
 +
| process 5 exposure    = &nbsp;
 +
| process 5 wafer type  = &nbsp;
 +
| process 5 wafer size  = 300 mm
 +
| process 5 transistor  = FinFET
 +
| process 5 volt        = &nbsp;
 +
| process 5 delta from  = [[28 nm]] Δ
 +
| process 5 fin pitch    = &nbsp;
 +
| process 5 fin pitch Δ  = &nbsp;
 +
| process 5 fin width    = &nbsp;
 +
| process 5 fin width Δ  = &nbsp;
 +
| process 5 fin height  = &nbsp;
 +
| process 5 fin height Δ = &nbsp;
 +
| process 5 gate len    = &nbsp;
 +
| process 5 gate len Δ  = &nbsp;
 +
| process 5 cpp          = &nbsp;
 +
| process 5 cpp Δ        = &nbsp;
 +
| process 5 mmp          = &nbsp;
 +
| process 5 mmp Δ        = &nbsp;
 +
| process 5 sram hp      = &nbsp;
 +
| process 5 sram hp Δ    = &nbsp;
 +
| process 5 sram hd      = &nbsp;
 +
| process 5 sram hd Δ    = &nbsp;
 +
| process 5 sram lv      = &nbsp;
 +
  | process 5 sram lv Δ    = &nbsp;
 +
  | process 5 dram        = &nbsp;
 +
  | process 5 dram Δ      = &nbsp;
 
}}
 
}}
−
{{scrolling table/mid}}
 
−
|-
 
−
! colspan="2" | [[Intel]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[GlobalFoundries]] !! colspan="2" | [[UMC]] !! colspan="2" | [[IBM]]
 
−
|- style="text-align: center;"
 
−
| colspan="2" | P1272 (CPU) / P1273 (SoC) || colspan="2" | 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info> || colspan="2" | 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info> || colspan="2" |  || colspan="2" |
 
−
|- style="text-align: center;"
 
−
| colspan="2" | 2014 || colspan="2" | 2015 || colspan="2" | 2015 || colspan="2" | 2017 || colspan="2" | 2015
 
−
|- style="text-align: center;"
 
−
| colspan="10" | FinFET
 
−
|- style="text-align: center;"
 
−
| colspan="8" | Bulk || colspan="2" | SOI
 
−
|- style="text-align: center;"
 
−
| colspan="10" | 300mm
 
−
|-
 
−
! Value !! [[22 nm]] Δ !! Value !! [[20 nm]] Δ !! Value !! [[20 nm]] Δ !! Value !! [[28 nm]] Δ !! Value !! [[22 nm]] Δ
 
−
|-
 
−
| 42 nm || 0.70x || 48 nm || rowspan="3" | N/A || 48 nm || rowspan="3" | N/A || ? nm || rowspan="3" | N/A || 42 nm || rowspan="3" | N/A
 
−
|-
 
−
| 8 nm || 1.00x || 8 nm || 8 nm || ? nm || 10 nm
 
−
|-
 
−
| 42 nm || 1.24x || ~38 nm || ~38 nm || ? nm || 25 nm
 
−
|-
 
−
| 20 nm || 0.77x || 30 nm || || 30 nm || || || || ||
 
−
|-
 
−
| 70 nm || 0.78x || 78 nm || 1.22x || 78 nm || 1.22x || ? nm || ?x || 80 nm || 0.80x
 
−
|-
 
−
| 52 nm || 0.65x || 64 nm || 1.00x || 64 nm || 1.00x || ? nm || ?x || 64 nm || 0.80x
 
−
|-
 
−
| rowspan="2" | 0.0588 µm² || rowspan="2" | 0.54x || 0.0806 µm² || ?x || 0.0806 µm² || ?x || ? µm² || ?x || 0.900 µm² ||
 
−
|-
 
−
| 0.064 µm² || ?x || 0.064 µm² || ?x || ? µm² || ?x || 0.081 µm² || 0.81x
 
−
|-
 
−
| || || || || || || ? µm² || ?x || 0.0174 µm² || 0.67x
 
−
{{scrolling table/end}}
 
 
=== Intel ===
 
=== Intel ===
 
[[File:intel 14nm gate.png|250px]]
 
[[File:intel 14nm gate.png|250px]]

Revision as of 03:06, 5 April 2017

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 14 nanometer (14 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 16 nm and 10 nm processes. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 14 nm process began in 2014. This technology is set to be replaced with 10 nm process in 2017.

Industry

14 nm became Intel's 2nd generation finFET transistors. This process became Samsungs' and GlobalFoundries first generation of finFet-based transistors. Intel uses TiN pMOS / TiAlN nMOS while Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Intel makes use of Self-Aligned Double Patterning (SADP) with 193 nm immersion lithography at critical patterning layers.


 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel Samsung GlobalFoundries IBM UMC
P1272 (CPU) / P1273 (SoC) 14LPE
1st generation; 14 nm Low Power Early
, 14LPP
2nd generation; 14 nm Low Power Performance
, 14LPC
3rd generation; 14 nm Low Power Cost [reduced]
, 14LPU
4th generation; 14 nm Low Power Ultimate
 14LPP
2nd generation; 14 nm Low Power Performance
    
2014        
         
         
         
Bulk Bulk Bulk SOI  
300 mm 300 mm 300 mm 300 mm 300 mm
FinFET FinFET FinFET FinFET FinFET
         
Value 22 nm Δ Value 20 nm Δ Value 20 nm Δ Value 22 nm Δ Value 28 nm Δ
42 nm 0.70x                
8 nm 1.00x                
42 nm 1.24x                
20 nm 0.77x                
70 nm 0.78x                
52 nm 0.65x                
0.0706 µm²                  
0.0499 µm²                  
0.0588 µm²                  
                   

Intel

intel 14nm gate.png

Find models

Click to browse all 14 nm MPU models

14 nm Microprocessors

This list is incomplete; you can help by expanding it.

14 nm Microarchitectures

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Documents

References

  • Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
  • Lin, C. H., et al. "High performance 14nm SOI FinFET CMOS technology with 0.0174 µm 2 embedded DRAM and 15 levels of Cu metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
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