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Difference between revisions of "2 µm lithography process"
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− | ! [[Intel]] || [[Intel]] || [[Toshiba]] || [[STMicro]] || [[Motorola]] || [[TI]] || [[AMD]] | + | ! [[Intel]] || [[Intel]] || [[Toshiba]] || [[STMicro]] || [[Motorola]] || [[TI]] || [[AMD]] || [[Hitachi]] |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | P414.1 (HMOS-II) || P421.X (HMOS-E) || || BCD-Offline || || || | + | | P414.1 (HMOS-II) || P421.X (HMOS-E) || || BCD-Offline || || || || Hi-CMOS II |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | 1980 || 1980 || 1986 || 1992 || || || | + | | 1980 || 1980 || 1986 || 1992 || || || || |
|- | |- | ||
− | | ? | + | | ? µm || ? µm || ? µm || ? µm || ? µm || ? µm || ? µm || 2 µm |
|- | |- | ||
− | | ? | + | | ? µm || ? µm || ? µm || ? µm || ? µm || ? µm || ? µm || 3 µm |
|- | |- | ||
| ? µm² || ? µm² || ? µm² || ? µm² || ? µm² || ? µm² || ? µm² | | ? µm² || ? µm² || ? µm² || ? µm² || ? µm² || ? µm² || ? µm² |
Revision as of 04:49, 4 April 2017
The 2 µm lithography process was the semiconductor process technology used by the some semiconductor companies in the mid to late 1980s. By the mid 80s this process was replaced by 1.5 µm, 1.3 µm, and 1.2 µm processes.
Industry
Fab |
---|
Process Name |
1st Production |
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell |
Intel | Intel | Toshiba | STMicro | Motorola | TI | AMD | Hitachi |
---|---|---|---|---|---|---|---|
P414.1 (HMOS-II) | P421.X (HMOS-E) | BCD-Offline | Hi-CMOS II | ||||
1980 | 1980 | 1986 | 1992 | ||||
? µm | ? µm | ? µm | ? µm | ? µm | ? µm | ? µm | 2 µm |
? µm | ? µm | ? µm | ? µm | ? µm | ? µm | ? µm | 3 µm |
? µm² | ? µm² | ? µm² | ? µm² | ? µm² | ? µm² | ? µm² |
Microprocessors
This list is incomplete; you can help by expanding it.
References
- Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.