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Difference between revisions of "130 nm lithography process"

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  |Contacted Gate Pitch
 
  |Contacted Gate Pitch
 
  |Interconnect Pitch (M1P)
 
  |Interconnect Pitch (M1P)
−
  |SRAM bit cell
+
  |SRAM bit cell (HP)​
 +
|SRAM bit cell (HD)​
 
}}
 
}}
 
{{scrolling table/mid}}
 
{{scrolling table/mid}}
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| colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2002 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2002 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" |  
 
| colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2002 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2002 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" |  
 
|- style="text-align: center;"
 
|- style="text-align: center;"
−
| colspan="8" | Bulk || colspan="4" | PDSOI || colspan="10" | Bulk
+
| colspan="8" | Bulk || colspan="2" | PDSOI || colspan="12" | Bulk
 
|- style="text-align: center;"
 
|- style="text-align: center;"
 
| colspan="2" | 6 || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" | 8 || colspan="2" | 8 || colspan="2" |  || colspan="2" | 5 || colspan="2" | 7 || colspan="2" | 6 || colspan="2" | 7
 
| colspan="2" | 6 || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" | 8 || colspan="2" | 8 || colspan="2" |  || colspan="2" | 5 || colspan="2" | 7 || colspan="2" | 6 || colspan="2" | 7
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! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ
 
! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ
 
|-
 
|-
−
| 319 nm || 0.66x || 310 nm || ?x || 350 nm || ?x || ? nm || ?x || 350 nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x
+
| 319 nm || 0.66x || 310 nm || ?x || 350 nm || ?x || ? nm || ?x || 350 nm || ?x || 350 nm || ?x || 350 nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x
 
|-
 
|-
−
| 345 nm || 0.69x || 340 nm || ?x || 350 nm || ?x || ? nm || ?x || 320 nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x
+
| 345 nm || 0.69x || 340 nm || ?x || 350 nm || ?x || ? nm || ?x || 320 nm || ?x || 350 nm || ?x || 350 nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x
 
|-
 
|-
−
| 2.0 µm² || 0.36x || 2.14 µm² || 0.46x || ? µm² || ?x || 1.98 µm² || 0.47x || 1.8 µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x  
+
| 2.45 µm² || ?x  || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x
 +
|-
 +
| 2.09 µm² || 0.36x || 2.14 µm² || 0.46x || ? µm² || ?x || 1.98 µm² || 0.47x || 1.8 µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x  
 
{{scrolling table/end}}
 
{{scrolling table/end}}
 
=== Design Rules ===
 
=== Design Rules ===
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** {{armh|ARM7|l=arch}}
 
** {{armh|ARM7|l=arch}}
 
{{expand list}}
 
{{expand list}}
 +
 +
== References ==
 +
* Tyagi, Sunit, et al. "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects." Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. IEEE, 2000.

Revision as of 19:32, 15 March 2017

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 130 nanometer (130 nm) lithography process is a full node semiconductor manufacturing process following the 150 nm process stopgap. Commercial integrated circuit manufacturing using 130 nm process began in 2001. This technology was replaced by with 110 nm process (HN) in 2003 and 90 nm process (FN) in 2004.

Industry

Fab
Process Name​
1st Production​
Type​
Metal Layers​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HP)​​
SRAM bit cell (HD)​
Intel TSMC Samsung Fujitsu IBM / Infineon / UMC Motorola AMD NEC NEC TI TI
P860 CS-91 CMOS 9S HiPerMOS 7
2001 2001 2001 2002 2001 2001 2002 2001 2001 2001
Bulk PDSOI Bulk
6 8 8 5 7 6 7
Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ
319 nm 0.66x 310 nm  ?x 350 nm  ?x  ? nm  ?x 350 nm  ?x 350 nm  ?x 350 nm  ?x  ?nm  ?x  ?nm  ?x  ?nm  ?x  ?nm  ?x
345 nm 0.69x 340 nm  ?x 350 nm  ?x  ? nm  ?x 320 nm  ?x 350 nm  ?x 350 nm  ?x  ?nm  ?x  ?nm  ?x  ?nm  ?x  ?nm  ?x
2.45 µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x
2.09 µm² 0.36x 2.14 µm² 0.46x  ? µm²  ?x 1.98 µm² 0.47x 1.8 µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x

Design Rules

130 nm Microprocessors

This list is incomplete; you can help by expanding it.

130 nm programmable logic devices

This list is incomplete; you can help by expanding it.

130 nm Microarchitectures

This list is incomplete; you can help by expanding it.

References

  • Tyagi, Sunit, et al. "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects." Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. IEEE, 2000.
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