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Difference between revisions of "5 nm lithography process"
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− | The '''5 nanometer (5 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 7 nm process is set to begin sometimes around 2021 or 2022. | + | The '''5 nanometer (5 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 7 nm process is set to begin sometimes around 2021 or 2022. The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to [[technology node|gate length or half pitch]]. |
== Initial research == | == Initial research == |
Revision as of 12:11, 24 December 2016
The 5 nanometer (5 nm) lithography process is a full node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2021 or 2022. The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch.
Initial research
- At the 2016 IEEE International Electron Devices Meeting (IEDM), researchers from CEA-Leti presented a paper detailing the architecture for a possible 5 nm node. The researchers presented their functional vertically stacked gate-all-around (GAA) silicon NW/NS (NanoWire/NanoSheet) MOSFETs. GAA NW transistors are a highly promising candidate to succeed FinFETs as the drive current can be optimized by vertically stacking multiple horizontal nanowires.
Industry
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5 nm Microprocessors
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5 nm Microarchitectures
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